SSD Controller Mapping for Overlap-Aware Soft Decoding
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Solution Overview
Problem
Current SSD devices based on MLC and TLC technologies face limitations in error correction capabilities, leading to poor reliability and high costs, especially in enterprise applications, due to increased bit errors and the need for multiple readings in LDPC decoding, which affects storage capacity and read access times.
Innovation Solution
A SSD controller with an encoding unit, mapping unit, demapping unit, and soft decoding unit that associates symbols with memory cells to maximize distance among threshold voltage distributions, using a 4-Dimensional mapping scheme and Quasi-Cyclic Low Density Parity Check (QC LDPC) codes to reduce bit errors and improve reliability, while marking failed memory pages to adjust allowed symbols and reduce storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC and TLC memory cell technologies are used to increase storage capacity, then the number of bits per memory cell increases, but the threshold voltage distributions overlap more, leading to increased bit errors and reduced reliability
Solution Approach 1:
The patent applies parameter changes by transforming the threshold voltage distributions through a mapping unit that redistributes the voltage levels. This mapping process optimizes the spacing between distributions to minimize overlap while maintaining the ability to store multiple bits per cell, thus reducing bit errors without sacrificing storage capacity
Solution Approach 2:
The patent replaces conventional reading mechanisms with a soft decoding approach using LDPC codes. Instead of relying solely on threshold voltage comparisons, the system uses error correction codes to detect and correct bit errors, substituting the mechanical voltage-threshold comparison process with a computational error correction mechanism
2Reliability
If LDPC decoding is used to improve error correction, then error correction capabilities improve, but multiple readings are required which increases complexity and cost
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing lookup tables during the programming phase. These tables contain pre-computed values that simplify the decoding process, allowing the system to avoid complex real-time calculations and reduce the number of readings required during error correction
Solution Approach 2:
The patent introduces an intermediary mapping unit that acts as a mediator between the memory cells and the decoding process. This mapping unit transforms the raw threshold voltage readings into optimized representations that are more suitable for LDPC decoding, reducing the complexity of the decoding operation
3Reliability
If enterprise-grade error correction is implemented, then reliability improves, but device cost increases
Solution Approach 1:
The patent applies universality by designing a controller architecture that can serve both consumer and enterprise applications with a single unified approach. The mapping unit and soft decoding unit work together to provide enterprise-grade reliability (UBER ≤ 10^-16) while maintaining cost-effectiveness through efficient use of resources and avoidance of redundant components
Data Source
AI summary
A controller for a solid state drive is proposed. The solid state drive comprises a plurality of memory cells, wherein each memory cell comprises a floating gate transistor for storing a symbol when programmed with a threshold voltage associated with that symbol, and wherein each threshold voltage is variable over the memory cells of the plurality of memory cells thereby defining a corresponding threshold voltage distribution. The controller comprises:an encoding unit for encoding information bits into encoded bits;a mapping unit for mapping the encoded bits into symbols to be stored, each one for being stored into a respective target memory cell, wherein the mapping comprises associating the symbols to be stored with the target memory cells in such a way that the threshold voltage distributions associated with said symbols to be stored define overlapping regions smaller than a predetermined overlapping region indicative of an admitted bit error rate;a demapping unit for demapping read symbols read from the target memory cells and providing metrics indicative of a distance between the threshold voltage distributions associated with the read symbols;a conversion unit for converting the metrics into an indication of the reliability of the read symbols; anda soft decoding unit for soft decoding the read symbols according to the indication of the reliability of the read symbols thereby obtaining the information bits.A corresponding solid state drive is also proposed.