SSD Controller Spreading Unit for Bit Error Rate Management

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Solution Overview

Problem

Solid State Drive (SSD) devices, particularly those using MLC and TLC technologies, face reduced lifetime and increased costs due to high bit error rates caused by narrow threshold voltage distributions, which overwhelm Forward Error Correction capabilities, leading to premature storage capacity reduction and high costs for enterprise applications.

Innovation Solution

A SSD controller with a spreading unit that marks memory pages with high bit error rates as failed, allowing only specific allowed symbols to be stored in associated memory cells to maximize threshold voltage distribution distance, and uses LDPC coding for error correction and decoding to extend SSD lifetime and reduce costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MLC and TLC technologies are used to increase storage capacity, then storage density is improved, but bit error rate increases due to narrow threshold voltage distributions

Engineering Contradiction:
Improvestorage capacityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory block is divided into multiple memory pages, and the controller selectively manages which pages are available for writing based on their error rates. This segmentation allows the system to maintain high storage capacity by utilizing healthy pages while isolating and protecting against errors in problematic pages, thereby resolving the contradiction between storage density and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller dynamically changes the parameter of symbol selection by determining allowed symbols that maximize threshold voltage distribution distance. This parameter change enables the system to adapt to the narrow threshold voltage distributions inherent in MLC and TLC technologies, maintaining low bit error rates while preserving high storage capacity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If Forward Error Correction is applied to correct bit errors, then reliability is improved, but storage capacity is reduced when memory blocks become unavailable

Engineering Contradiction:
Improveerror correction capabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The controller performs preliminary assessment of memory page error rates before allowing writes to those pages. By proactively identifying and marking problematic pages as failed before they cause complete block failure, the system maintains reliability through early error detection while preserving storage capacity by keeping healthy pages available for use.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the set of allowed symbols based on the specific error characteristics of each memory page. This dynamic adaptation enables the controller to optimize the balance between error correction and storage capacity utilization, allowing the system to maintain high reliability while maximizing available storage space by flexibly managing which pages and symbols are usable.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If threshold voltage distributions are spaced closer to increase storage density, then storage capacity is improved, but cell-to-cell interference increases causing more bit errors

Engineering Contradiction:
Improvestorage densityVSAvoidcell-to-cell interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The controller applies local quality management by determining allowed symbols specifically for groups of memory cells associated with failed pages, rather than uniformly managing all cells. This localized approach allows the system to maintain high storage density through close threshold voltage spacing while compensating for cell-to-cell interference in specific problematic areas through targeted symbol selection.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system changes the parameter of threshold voltage distribution utilization by selecting allowed symbols that maximize distance among distributions. This parameter change enables the system to operate effectively with closely spaced threshold voltage distributions by adaptively choosing symbols that are least susceptible to cell-to-cell interference, thereby maintaining high storage density while mitigating error rates.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If entire memory blocks are marked as failed to ensure data integrity, then reliability is improved, but storage capacity is drastically reduced

Engineering Contradiction:
Improvedata integrityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The controller segments the memory block into individual pages and selectively marks only the problematic pages as failed while keeping the rest of the block available. This granular segmentation prevents the cascading failure of entire blocks, maintaining data integrity through targeted page-level management while preserving the majority of storage capacity in healthy pages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies partial action by determining allowed symbols for only the specific groups of memory cells associated with failed pages, rather than applying error correction uniformly across the entire block. This partial approach ensures data integrity in affected areas while avoiding unnecessary capacity loss in healthy areas, optimizing the balance between reliability and storage capacity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9715908B2Controller for a solid-state drive, and related solid-state drive
Publication Date: 2017.07.25 NANDEXT SRL
  • US9715908B2 patent drawing
  • US9715908B2 patent drawing
  • US9715908B2 patent drawing

AI summary

A controller for a solid state drive is proposed. The solid state drive comprises a plurality of memory cells each one storing a symbol among a plurality of possible symbols. Each bit of each symbol is associated with a respective memory page. The controller comprisesa spreading unit configured tomark a memory page whose bit error rate overruns an admitted bit error rate as a failed memory page, or as an unfailed memory page otherwise, and todetermine allowed symbols that are allowed to be stored in a group of memory cells associated with the failed memory page. The allowed symbols are a subset of the possible symbols such that the bits of the allowed symbols associated with the unfailed memory pages include all possible bit combinations. The controller comprisesa writing unit configured to write information bits into the group of memory cells according to the allowed symbols.