SSD Controller Volatile Memory Data Integrity

Solution Overview

Problem

The use of cyclic redundancy check codes and error-correcting codes in volatile memory systems like DRAM increases the number of instructions required for data access, leading to reduced throughput and system performance.

Innovation Solution

The SSD controller in a memory device generates cyclic redundancy check codes and error-correcting codes and stores them sequentially or alternately with the data in the volatile memory, reducing the need for frequent row address replacements and thereby minimizing the number of instructions required for data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cyclic redundancy check codes and error-correcting codes are added to ensure data correctness, then data reliability is improved, but the number of instructions for accessing volatile memory increases, reducing throughput

Engineering Contradiction:

Improvedata correctnessVSAvoidDRAM throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges the storage of data and check codes into a unified memory structure where data and its corresponding cyclic redundancy check code are stored in the same row of the volatile memory. This combining approach allows both data and verification codes to be accessed simultaneously in a single memory operation, eliminating the need for separate access instructions and thereby maintaining high throughput while ensuring data reliability through integrated error checking

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary generation of cyclic redundancy check codes during the data writing phase, before data retrieval operations. The SSD controller generates the check code when data is first written to volatile memory, so that when data is later read, the check code is already available in the same memory row, eliminating the need for additional computation instructions during data access and thus maintaining high throughput

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If check codes are stored separately from data, then data and check code management is simplified, but frequent row address replacements are required, increasing the number of instructions

Engineering Contradiction:

Improvedata managementVSAvoidaccess instruction count

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent merges the storage of data and check codes into a unified memory structure where data and its corresponding cyclic redundancy check code are stored in the same row of the volatile memory. This combining approach allows both data and verification codes to be accessed simultaneously in a single memory operation, eliminating the need for separate access instructions and thereby maintaining high throughput while ensuring data reliability through integrated error checking

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11360853B2Access method

Publication Date: 2022.06.14 SILICON MOTION INC

AI summary

An access method is provided, which is applied to a memory device. The memory device is coupled to a host device, the host device is configured to provide a data, the memory device includes a SSD controller and a volatile memory, the volatile memory is coupled to the SSD controller, and the volatile memory includes a data storage area. The access method includes: the SSD controller receiving the data, the SSD controller generating a corresponding cyclic redundancy check code according to the data, and the SSD controller sequentially storing the data and the cyclic redundancy check code into the data storage area.