SSD Write Buffer Release Using Cross-Page ECC
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Solution Overview
Problem
The write performance of solid-state drives (SSDs) is hindered by the insufficient size of the write buffer, leading to degraded performance due to insufficient storage capacity, which also increases power consumption and costs.
Innovation Solution
A memory system comprising a volatile write buffer, nonvolatile NAND flash memory, and a controller that employs error correction codes (ECC) to efficiently manage data transfer and storage, allowing for early release of buffer space by generating and using Level 3 ECC (L3ECC) to correct errors across multiple pages and chips, thereby optimizing buffer utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the write buffer size is reduced to lower power consumption and costs, then power consumption and costs decrease, but write performance degrades due to insufficient storage capacity
Solution Approach 1:
The patent segments the write buffer into multiple independent buffer units (first write buffer, second write buffer, etc.) that can operate independently. This allows the system to manage data writing in smaller chunks, releasing buffer space incrementally as data is written to NAND flash memory, thereby maintaining adequate buffering capacity while reducing the total buffer size required.
Solution Approach 2:
The controller performs preliminary error correction code generation (L3ECC) on data before it is fully written to the NAND flash memory. By generating L3ECC for partial data sets and storing this correction information in the buffer, the system enables early release of buffer space while ensuring data integrity can be maintained even with reduced buffer capacity.
2Ease of manufacture
If the write buffer size is reduced to lower costs, then manufacturing costs decrease, but write performance degrades due to insufficient storage capacity
Solution Approach 1:
The write buffer is divided into multiple smaller buffer units that can be implemented with reduced total memory capacity. This segmentation allows the system to achieve adequate write performance through parallel processing and incremental data release, thereby reducing the overall buffer size and manufacturing costs while maintaining functionality.
Solution Approach 2:
The system changes the error correction approach by implementing L3ECC (Level 3 Error Correction Code) that operates on segmented data portions. This parameter change in error correction methodology allows the system to maintain data integrity with smaller buffer sizes, enabling cost reduction without sacrificing write performance.
3Reliability
If data is held in the write buffer until all data is written to NAND flash memory, then data integrity is maintained, but buffer space cannot be released early, degrading write performance
Solution Approach 1:
The controller performs preliminary error correction code generation (L3ECC) on data portions before complete writing to NAND flash memory. This preliminary action creates redundancy information that allows the system to verify and release data incrementally, enabling early buffer space release while maintaining data integrity through the generated correction codes.
Solution Approach 2:
The system implements a feedback mechanism where the controller monitors the writing status of data to NAND flash memory and uses the generated L3ECC information to determine when buffer space can be safely released. This feedback loop ensures data integrity is maintained while enabling dynamic buffer management that improves write performance.
Data Source
AI summary
According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.