SSD Controller Decoding with Parallel Bit Flipping Thresholds
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Solution Overview
Problem
Existing SSD storage devices face challenges in improving reading speed and service life due to limitations in decoding speed and error correction capabilities of error correction algorithms.
Innovation Solution
A decoding method that optimizes the calculation of check equations not met by each bit, introduces a threshold determining mechanism for simultaneous calculation and bit flipping, and uses a random sequence generator to control bit flipping probabilities, thereby reducing decoding delays and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional error correction algorithms are used, then decoding accuracy is maintained, but decoding speed is slow and decoding delay is high
Solution Approach 1:
The patent segments the bit sequence into multiple groups and processes them in parallel using multiple processing units. Each processing unit handles a specific group of bits simultaneously, dividing the overall decoding task into smaller independent sub-tasks that can be executed concurrently, thereby increasing decoding speed and reducing delay
Solution Approach 2:
The patent implements dynamic bit flipping strategies where the flipping decision is based on real-time syndrome calculation results. The system dynamically adjusts which bits to flip based on the current error pattern detected, rather than using fixed predetermined flipping sequences, optimizing the decoding process adaptively
2Reliability
If aggressive bit flipping is performed to correct errors, then error correction capability is improved, but the probability of incorrectly flipping correct bits increases
Solution Approach 1:
The patent uses syndrome calculation as a feedback mechanism to guide bit flipping operations. After each flipping operation, the system recalculates the syndrome to verify whether the error has been corrected. This feedback loop ensures that flipping operations are performed only when necessary and validates the correctness of each flipping action, preventing incorrect modifications to already correct bits
Solution Approach 2:
The patent performs preliminary syndrome calculation on the received bit sequence before any bit flipping operations. This preliminary assessment identifies which bits are likely erroneous based on the syndrome pattern, allowing the system to target flipping operations only at the most probable error locations rather than randomly or aggressively flipping bits throughout the sequence
3Productivity
If sequential processing of check equations is used, then calculation accuracy is maintained, but processing throughput is limited
Solution Approach 1:
The patent divides the check equation processing into multiple parallel streams, with each processing unit handling a specific subset of check equations simultaneously. This segmentation of the processing workload across multiple independent units enables concurrent execution of check equation validations, significantly increasing throughput while maintaining the logical structure of sequential verification within each parallel stream
Solution Approach 2:
The patent designs processing units that can universally handle different types of check equations and bit groups using the same fundamental processing logic. Each processing unit is configured to perform syndrome calculation, bit flipping decisions, and verification operations on various data segments, allowing the system to maintain consistent accuracy standards across all processing paths while benefiting from parallel execution
Data Source
AI summary
A decoding method includes a threshold determining mechanism such that that a controller chip can simultaneously perform calculation of a quantity of check equations that are not met by a bit and a bit flipping process. In addition, an algorithm for calculating the quantity of check equations that are not met by each bit is optimized.