SSD Deduplication Circuit Buffer Reordering

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Solution Overview

Problem

Solid state drives (SSDs) face challenges with write amplification and over-provisioning due to asymmetric write and erase granularities, leading to inefficiencies in data storage and performance.

Innovation Solution

Implementing a deduplication control circuit in SSDs that identifies and reorders data content, using headers and pointers to eliminate duplicate data storage, thereby reducing the amount of data written and optimizing storage efficiency without altering the flash storage format or garbage collection policies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data deduplication is implemented in SSDs, then storage efficiency is improved and write amplification is reduced, but device complexity increases due to the need for deduplication control circuits and buffer management

Engineering Contradiction:
Improvestorage efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer is divided into multiple segments or regions, allowing the deduplication control circuit to manage data in smaller, organized units. This segmentation enables efficient tracking of duplicate data while maintaining overall system simplicity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The deduplication control circuit performs preliminary analysis of incoming data before it is fully written to storage by checking for duplicates in the buffer using hash values. This preliminary action identifies duplicate data early, preventing redundant storage operations and reducing write amplification before it occurs.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If duplicate data is eliminated through buffering and reordering, then write amplification is reduced, but loss of time occurs due to additional processing steps for counting, comparing, and reordering data

Engineering Contradiction:
Improvewrite amplificationVSAvoidprocessing time
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

Hash values are calculated and compared in advance during the data buffering phase, allowing duplicate detection to occur before final storage commitment. This preliminary action enables the system to identify and skip duplicate writes without delaying the overall write operation timeline.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

When duplicate data is detected through hash comparison, the system skips the redundant buffering and writing steps for that data. The deduplication control circuit rapidly identifies duplicates and bypasses unnecessary processing stages, reducing the time penalty associated with deduplication operations.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Speed

If data is buffered and reordered to group contents near headers, then read performance is improved, but device complexity increases due to buffer reordering mechanisms

Engineering Contradiction:
Improveread performanceVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Related data elements (headers and their corresponding data contents) are merged into contiguous memory regions within the buffer. This merging ensures that when data is read, the header and associated content are located near each other, improving read performance without requiring complex reordering mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The buffer is organized with local optimization where each header is positioned adjacent to its corresponding data content. This local quality arrangement ensures that read operations can efficiently access both metadata and data without traversing large distances in memory, improving speed while maintaining simple buffer management.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11042316B1Reordered data deduplication in storage devices
Publication Date: 2021.06.22 SEAGATE TECH LLC
  • US11042316B1 patent drawing
  • US11042316B1 patent drawing
  • US11042316B1 patent drawing

AI summary

A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.