SSD Drain Buffer for PCIe Packet Management

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Solution Overview

Problem

Existing systems lack an efficient mechanism for draining unnecessary PCIe packets, leading to potential issues such as command buildup and unauthorized transactions in multi-function devices.

Innovation Solution

The implementation of a drain buffer per physical or virtual function in a solid state drive (SSD), along with logic to generate traffic, allows the controller to funnel unnecessary packets to a host and back to the memory device, effectively draining them by ignoring them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If peer-to-peer PCIe transactions are enabled without ACS, then transaction speed is improved, but system security deteriorates due to unauthorized transactions

Engineering Contradiction:
Improvetransaction speedVSAvoidsystem security
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The drain buffer acts as an intermediary component between PCIe endpoints and the host system. It intercepts and absorbs unauthorized or unnecessary peer-to-peer transactions, preventing them from reaching their intended targets while allowing legitimate transactions to proceed. This mediator approach resolves the contradiction by enabling fast peer-to-peer transactions while maintaining security through the buffer's filtering capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If ACS is enabled to prevent unauthorized transactions, then system security is improved, but transaction overhead increases due to root complex involvement

Engineering Contradiction:
Improvesystem securityVSAvoidtransaction overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The drain buffer implements local quality by providing security-specific functionality at the endpoint level rather than requiring all transactions to traverse the root complex. The buffer is locally configured at each PCIe endpoint to handle security concerns, allowing most transactions to proceed locally without root complex involvement, thus reducing overhead while maintaining security.

Inventive Principle:
Principle #3Local quality

3Productivity

If drain buffer is added to SSD, then command draining capability is improved, but device complexity increases

Engineering Contradiction:
Improvecommand draining capabilityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The drain buffer is designed with multi-functionality to justify its addition to the SSD. It serves multiple purposes: draining unnecessary commands, absorbing peak transaction loads, providing security filtering, and enabling peer-to-peer transactions. This universal approach allows a single component to address multiple issues, making the increased device complexity worthwhile by delivering substantial productivity improvements in command handling.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250156347A1Peer-To-Peer Communication Using Drain Buffers In Multi-Function Device
Publication Date: 2025.05.15 SANDISK TECHNOLOGIES LLC
  • US20250156347A1 patent drawing
  • US20250156347A1 patent drawing
  • US20250156347A1 patent drawing

AI summary

Instead a having a system that lacks command draining, add a drain buffer to the solid state drive (SSD) to optimize command usage. By adding a drain buffer per physical function (PF) or virtual function (VF) and utilizing logic that can generate traffic, the controller is able to funnel packets to a host if the packet is not needed. The controller will change the original address of the packet to a different address. The controller will then send that packet with the different address through the host and back to the memory device. The packet will be in a different function, but the controller will know not to access the packet or ignore the packet. Ignoring the packet will act as a drain for the SSD. The controller PCIe packets draining occur in special flows, dummy traffic generation for PCIe attribute measurements, and internal events posting over the host/device interface.