SSD DRAM Reduction via Referring Table Subgroup Mapping

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Solution Overview

Problem

The increasing storage capacity of SSDs leads to a significant increase in the cost of the required DRAM module, which is typically at least 1/1000 of the total storage capacity, making it an unavoidable expense.

Innovation Solution

A method is introduced that reduces DRAM usage in SSDs by utilizing a referring table in the DRAM module to store physical addresses of subgroups of the mapping table in non-volatile memory units, allowing for efficient access and reducing the need to copy the entire mapping table from flash memory to DRAM, thereby minimizing DRAM size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the storage capacity of SSD is increased, then the storage capacity is improved, but the cost of DRAM module increases significantly

Engineering Contradiction:

Improvestorage capacityVSAvoidDRAM module cost

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The mapping table is divided into multiple subgroups, where only the currently needed subgroup is loaded into DRAM while other subgroups remain in flash memory. This segmentation allows the system to handle large storage capacities without proportionally increasing DRAM size, thus reducing cost while maintaining performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of loading the entire mapping table into DRAM, only the necessary portion (current subgroup) is loaded. This partial action approach reduces DRAM requirements significantly while still providing fast access for current operations, addressing the cost issue without sacrificing functionality.

Inventive Principle:

Principle #16Partial or excessive action

2Speed

If the entire mapping table is copied from flash memory to DRAM, then read/write speed is improved, but DRAM size and cost increase

Engineering Contradiction:

Improveread/write speedVSAvoidDRAM size

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The mapping table is segmented into subgroups, and only the active subgroup is copied to DRAM at any given time. This maintains fast read/write speeds for current operations while keeping DRAM size minimal, avoiding the need to allocate large DRAM capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Only the necessary subgroup of the mapping table is loaded into DRAM rather than the entire table. This partial loading strategy achieves fast access speeds for current operations without requiring excessive DRAM capacity, thus resolving the contradiction between speed and size.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If a small DRAM module is used, then cost is reduced, but access speed to mapping data decreases

Engineering Contradiction:

ImproveDRAM module costVSAvoidmapping data access speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The needed subgroup of the mapping table is pre-loaded into DRAM before it is actually needed for operations. This preliminary action ensures that when read/write operations occur, the data is already in fast DRAM, maintaining high access speeds despite using minimal DRAM capacity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

By loading only the necessary subgroup into DRAM in advance, the system achieves fast access speeds for current operations without requiring large DRAM capacity. This partial pre-loading strategy balances cost and performance effectively.

Inventive Principle:

Principle #16Partial or excessive action

4Reliability

If the DRAM module size is reduced, then cost is reduced, but the ability to store complete mapping table is compromised

Engineering Contradiction:

ImproveDRAM module costVSAvoidmapping table storage capacity

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The mapping table is divided into subgroups stored in flash memory, with only the active subgroup in DRAM. This segmentation allows the complete mapping table to be maintained in flash (inexpensively) while keeping DRAM minimal, resolving the contradiction between storage capacity and cost.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Flash memory acts as an intermediary storage layer that holds the complete mapping table when not in use. This allows DRAM to be kept small while still providing access to the full mapping table through the flash memory intermediary, balancing cost and capacity requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10108342B2Method for reducing use of DRAM in SSD and the SSD using the same

Publication Date: 2018.10.23 STORART TECHSHENZHEN CO LTD

AI summary

A SSD and a method for reducing use of DRAM in the SSD are disclosed. The method includes the steps of: A. providing a referring table in a DRAM module of a SSD; B. providing a logical-to-physical address table in the DRAM module; C. receiving a command for accessing a target data in a target logical address of the SSD; D. checking if one physical address is stored in the logical-to-physical address table; E. executing the command by using the mapping data in the subgroup or copying a corresponding subgroup including one mapping data for the target logical address from the mapping table to the DRAM module via the referring table; and; and F. adding a target physical address of the DRAM module where the mapping data for the target logical address is stored to the logical-to-physical address table so that the target logical address is able to correspond thereto.