SSD Dual ECC Architecture for High-Bit-Error Data Recovery
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Solution Overview
Problem
Current storage devices, such as solid state drives (SSDs), are limited in their ability to correct bit errors, leading to data loss when the number of errors exceeds the threshold value, as they rely solely on error detection and correction codes (EDC and ECC) which have limitations in error correction capacity.
Innovation Solution
The implementation of a storage device with both a controller ECC engine and die ECC engines, where the controller generates initial ECC/EDC data and sends it to dies for storage as code words, with each die generating additional ECC/EDC data to correct errors up to a threshold, and the controller correcting errors beyond this threshold using a speculative code word.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only controller-level ECC is used for error correction, then device complexity is reduced, but error correction capability is insufficient when bit errors exceed the threshold value
Solution Approach 1:
The ECC functionality is segmented into two levels: controller-level ECC engine and die-level ECC engines. The controller ECC engine handles overall error correction for the storage device, while individual die ECC engines handle error correction at the die level. This segmentation allows error correction capability to be distributed across multiple independent units, improving overall reliability without requiring a single complex centralized ECC system.
Solution Approach 2:
The die ECC engines are nested within the storage device structure, with each die containing its own ECC engine. The controller ECC engine then encompasses and coordinates these nested die-level ECC engines. This nested architecture allows the system to leverage both the localized error correction capability of individual dies and the global error correction capability of the controller, achieving enhanced error correction without linearly increasing overall system complexity.
2Reliability
If multiple ECC engines are implemented at both controller and die levels, then data protection is enhanced, but device complexity increases
Solution Approach 1:
The ECC protection system is segmented into controller-level and die-level components, each handling specific aspects of error correction. This segmentation allows the system to achieve comprehensive data protection through coordinated operation of multiple ECC engines while maintaining manageable complexity by distributing functions across different levels of the storage device hierarchy.
Solution Approach 2:
The ECC engines at both controller and die levels perform similar error correction functions but operate at different granularities. This multi-functionality approach allows the system to use the same fundamental ECC technology uniformly across different levels, simplifying the overall design while achieving enhanced protection. The universal ECC mechanism can handle various error patterns at both local and global levels.
Data Source
AI summary
The present disclosure generally relates to storage devices, such as solid state drives. A storage device comprises a controller comprising a controller error correction code (ECC) engine and a storage unit comprising a plurality of dies. Each of the dies comprise a die ECC engine. When user data is received, the controller ECC engine generates first ECC/error detection code (EDC) data. The user data and the first ECC/EDC data is sent to a die for storage as a code word. The die ECC engine generates second ECC/EDC data for the code word in granular portions. The second ECC/EDC data is used to correct bit errors in one or more code words up to a threshold value. When the number of bit errors exceeds the threshold value, the failed code words are sent to the controller ECC engine for correction.