SSD ECC Decoder Pooling for Interleaved Multi-Frame Decoding

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional non-volatile memory controllers with dedicated ECC decoders for each sub-code in SSDs operate inefficiently, as they decode frames sequentially, leading to prolonged data decoding times and underutilization of sub-decoders.

Innovation Solution

Implementing a system where ECC decoders are pooled and frames are interleaved and alternated between sub-decoders, allowing simultaneous decoding of multiple frames across different memory channels, optimizing the use of sub-decoders and reducing overall decoding time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated ECC decoders are used for each memory channel, then data integrity and reliability are maintained, but decoding efficiency and resource utilization are reduced

Engineering Contradiction:

Improvedata integrityVSAvoiddecoding efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements pooled ECC decoders that can serve multiple memory channels instead of dedicated decoders for each channel. The same decoder resources are shared across channels 0-7, allowing one decoder to process frames from any channel, thereby improving resource utilization while maintaining the required data integrity through proper error correction coding

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If sequential decoding is performed for each frame, then decoding accuracy is maintained, but total decoding time increases

Engineering Contradiction:

Improvedecoding accuracyVSAvoidtotal decoding time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements interleaved decoding where multiple frames are decoded in parallel across available decoders. While one decoder processes frame N, another decoder simultaneously processes frame N+1, ensuring continuous utilization of decoder resources. This parallel processing maintains decoding accuracy while significantly reducing the total time required to decode all frames compared to sequential processing

Inventive Principle:

Principle #20Continuity of useful action

3Productivity

If sub-decoders are pooled for multi-channel support, then resource utilization improves, but frame interleaving complexity increases

Engineering Contradiction:

Improveresource utilizationVSAvoidframe interleaving complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the decoding process into distinct phases: frame reception and buffering, decoder allocation based on availability, interleaved processing across multiple decoders, and result consolidation. This segmentation of the complex interleaving process into manageable stages reduces the overall complexity while enabling efficient pooled decoder utilization across multiple memory channels

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10886947B2Efficient decoding of n-dimensional error correction codes

Publication Date: 2021.01.05 KIOXIA CORP

AI summary

Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).