SSD Error Correction Decoder Selection for Read Latency Control

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Solution Overview

Problem

Current solid-state drive (SSD) systems face inefficiencies in error correction, garbage collection, data write operations, power distribution, and wear leveling, which can lead to increased latency, reduced performance, and shorter SSD lifespan due to inadequate control over NAND memory states and power management.

Innovation Solution

The implementation of an extended command and status signal system between the host device and SSD controller allows for dynamic control of error correction, garbage collection, data write operations, power distribution, and wear leveling by providing detailed attributes and status information, enabling the host device to optimize SSD operations based on real-time conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction processing is performed on read data from NAND memory, then data reliability is improved, but read latency increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary error correction processing on read data before data transfer to the host device. The controller initiates error correction in advance during the read operation, so that when data is transferred to the host, correction is already complete or underway, reducing the perceived latency while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The error correction process operates continuously during data reads rather than as a separate post-processing step. The controller maintains continuous error correction processing on read data streams, ensuring that correction is always active and reducing idle time between read operations and error correction completion.

Inventive Principle:
Principle #20Continuity of useful action

2Reliability

If garbage collection is performed to manage NAND memory blocks, then storage reliability is improved, but write performance deteriorates

Engineering Contradiction:
Improvestorage reliabilityVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller performs garbage collection periodically during idle periods or low-utilization times rather than continuously interrupting write operations. This periodic execution of garbage collection maintains storage reliability by cleaning up invalid data while minimizing interference with active write performance.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The controller proactively identifies and prepares garbage collection candidates in advance, organizing invalid data for collection before it impacts write performance. By preparing garbage collection tasks preliminarily during idle periods, the system maintains storage health without causing performance degradation during active writes.

Inventive Principle:
Principle #10Preliminary action

3Duration of action of stationary object

If wear leveling is implemented to distribute write operations, then SSD lifespan is extended, but write complexity increases

Engineering Contradiction:
ImproveSSD lifespanVSAvoidwrite complexity
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The controller implements self-managing wear leveling by automatically tracking and distributing write operations across NAND blocks without requiring external intervention. The system autonomously monitors block usage and redirects writes to extend lifespan, handling the complexity internally while presenting a simple interface to the host device.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The controller uses feedback mechanisms to monitor NAND block wear levels and dynamically adjust write distribution. By continuously monitoring block status and providing feedback to the write management system, the controller optimizes wear leveling while maintaining relatively simple operational complexity through adaptive control.

Inventive Principle:
Principle #23Feedback

4Adaptability or versatility

If dynamic control of SSD operations is implemented through extended commands, then system adaptability is improved, but interface complexity increases

Engineering Contradiction:
Improvesystem adaptabilityVSAvoidinterface complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The controller implements a universal extended command interface that handles multiple SSD operations (error correction control, garbage collection management, wear leveling adjustment) through a single standardized command structure. This multi-functional approach improves system adaptability across different operations while maintaining interface simplicity through consolidation rather than proliferation of separate commands.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system employs dynamic command execution where the controller adapts operation parameters in real-time based on current SSD state and host requirements. The extended command interface allows dynamic adjustment of error correction intensity, garbage collection timing, and wear leveling strategies without requiring complex static configuration, improving adaptability through runtime flexibility.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12131024B2Memory system, host device and information processing system for error correction processing
Publication Date: 2024.10.29 KIOXIA CORP
  • US12131024B2 patent drawing
  • US12131024B2 patent drawing
  • US12131024B2 patent drawing

AI summary

A memory system including: a nonvolatile memory; first and second decoders configured to execute first and second error correction for correcting data read from the nonvolatile memory; and a controller configured to receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command, and after receiving the first command, output data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.