SSD Error Correction and Bad-Block Remapping for MLC Flash
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional approaches to error management in flash memory, particularly in multi-level cell (MLC) flash memories, are inefficient in achieving low uncorrectable error rates over the total service life and traffic loads required in enterprise storage environments, leading to degradation in signal-to-noise ratio and reduced reliability.
Innovation Solution
The techniques involve grouping flash memory pages across multiple dies and managing them to reduce error floors and flares, allowing operation in error regimes that would otherwise produce unacceptably high post-correction errors, and moving the block remapping function into the error correction domain, eliminating the need for tables used to avoid bad blocks, thereby enhancing reliability and reducing overprovisioning, throughput, power, and endurance impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BCH error correction coding is used in MLC flash memory, then the implementation is simple and cost-effective, but the uncorrectable error rate becomes unacceptably high over the device service life in enterprise storage environments
Solution Approach 1:
The error correction function is segmented into two independent layers: a primary BCH decoder for fast correction of common errors, and a secondary LDPC decoder for correcting residual errors. This segmentation allows each decoder to be optimized for its specific error regime, achieving enterprise-grade reliability without requiring a single complex decoding system
Solution Approach 2:
The patent introduces an intermediary error estimation mechanism that assesses the error rate after BCH decoding and determines whether LDPC decoding is necessary. This intermediary step acts as a gatekeeper, activating the complex LDPC decoder only when needed, thus achieving high reliability while minimizing the average complexity and power consumption
2Quantity of substance
If flash memory density is increased with decreasing process technology, then storage capacity improves, but signal-to-noise ratio decreases due to reduced charge storage, increased crosstalk, and thinner insulation materials
Solution Approach 1:
The patent dynamically changes the error correction parameters (BCH code strength, LDPC code rate) based on the estimated error rate, which itself is derived from the signal quality metrics. This adaptive parameter adjustment allows the system to maintain optimal reliability across varying signal-to-noise ratios caused by different memory densities and aging conditions
3Ease of manufacture
If MLC flash memory is used instead of SLC, then cost is reduced and storage density is increased, but program/erase cycle lifetime is significantly reduced
Solution Approach 1:
The patent applies beforehand cushioning by implementing a conservative error rate threshold that triggers LDPC decoding earlier in the error progression. This proactive approach compensates for the reduced lifetime of MLC cells by ensuring errors are corrected before they accumulate to uncorrectable levels, effectively extending the usable life of MLC memory in enterprise applications
Data Source
AI summary
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.