Cooperative SSD Error Recovery for Low-Latency ECC
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Solution Overview
Problem
Distributed computing systems face high latency due to the use of solid-state drives (SSDs) with advanced flash memory technologies like TLC and QLC, which are prone to higher bit-error rates, necessitating complex and power-consuming error-correcting code (ECC) methods.
Innovation Solution
A cooperative error correction approach where data storage drives and a storage host work together to correct errors, employing iterative ECC schemes between the drives and the host, allowing the host to control latency by selecting appropriate error correction processes and utilizing parity and user data from multiple drives for correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex ECC methods are used to correct errors in TLC/QLC flash memory, then error correction capability is improved, but latency increases
Solution Approach 1:
The error correction function is segmented between the SSD controller (performing initial ECC) and the storage host (performing additional error correction). This division allows the SSD to quickly handle simple errors while the host provides supplementary correction capability, reducing overall latency compared to relying solely on complex host-based ECC.
Solution Approach 2:
The SSD controller performs preliminary error correction using ECC codes before data is transferred to the host. This preliminary action corrects many errors upfront, reducing the burden on the host and minimizing the time required for any additional host-based error correction operations.
2Reliability
If complex ECC algorithms are implemented, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The error correction workload is segmented between the SSD controller and the storage host. The SSD controller handles initial ECC operations with lower power consumption, while the host performs additional correction only when needed, reducing total power consumption compared to implementing full complex ECC functionality in the SSD.
Solution Approach 2:
The SSD controller performs self-service error correction using built-in ECC capabilities before data leaves the drive. This self-service approach corrects many errors at the source with minimal power consumption, reducing the need for power-intensive host-based correction operations.
3Reliability
If robust ECC methods are used for TLC/QLC flash, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The error correction system is segmented between the SSD controller (with basic ECC circuits) and the storage host (with additional correction capabilities). This segmentation allows the SSD to use simpler, less complex circuits while the host provides enhanced correction functionality, reducing overall system complexity compared to implementing all correction features in the SSD.
Solution Approach 2:
The storage host acts as an intermediary that provides additional error correction capability without requiring complex circuits to be built into the SSD. The host receives data from the SSD and performs supplementary error correction, enabling robust error correction with minimal increase in SSD device complexity.
Data Source
AI summary
In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.