Single-Port SSD Failover via Host Selection and Lane Reversal
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Solution Overview
Problem
Conventional failover mechanisms for solid-state drives (SSDs) in enterprise applications are costly due to the need for dual-port SSDs or expensive PCIe switches, which are not feasible for single-port SSDs to provide high availability without compromising size and cost.
Innovation Solution
A failover mechanism is implemented using a single-port SSD with a flash memory controller, a multiplexer, and a control logic circuit that selects between two hosts based on a selection signal, allowing only one host to access the SSD at a time, and enables lane reversal to switch access in case of host failure, eliminating the need for a PCIe switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual-port SSD is used to provide failover mechanism, then high availability is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The single flash memory controller is designed to serve multiple hosts (first host and second host) sequentially. The controller can switch between handling commands from different hosts through the same connector, making a single controller perform the function that would traditionally require two separate controllers in a dual-port SSD configuration.
Solution Approach 2:
The patent merges the functionality of two separate flash memory controllers (one for each host) into a single controller that can time-division multiplex between hosts. This consolidation eliminates the need for duplicate controller hardware, reducing manufacturing cost while maintaining failover capability through host switching.
2Reliability
If a PCIe switch is added to enable single-port SSD to communicate with two hosts, then failover mechanism is achieved, but device size increases and manufacturing cost increases
Solution Approach 1:
The patent extracts the PCIe switch component from the SSD device entirely. Instead of including a PCIe switch within the SSD to enable dual-host communication, the solution uses the existing connector to directly connect the flash memory controller to multiple hosts through lane reversal, eliminating the need for additional switching hardware inside the device.
Solution Approach 2:
Rather than adding a PCIe switch to route signals from multiple hosts to a single controller (the conventional approach), the patent inverts the approach by having the single controller directly communicate with multiple hosts through the same connector using lane reversal technology. This reverses the traditional signal routing architecture.
3Reliability
If a PCIe switch is added to enable single-port SSD to communicate with two hosts, then failover mechanism is achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces the expensive PCIe switch component with a more cost-effective lane reversal mechanism that uses existing connector infrastructure. This substitution uses simpler, cheaper hardware that achieves the same failover functionality without the high cost of dedicated switching components.
Solution Approach 2:
The single flash memory controller is designed to serve multiple hosts (first host and second host) sequentially. The controller can switch between handling commands from different hosts through the same connector, making a single controller perform the function that would traditionally require two separate controllers in a dual-port SSD configuration.
4Reliability
If lane reversal is implemented for host switching, then seamless failover is achieved, but control complexity increases
Solution Approach 1:
The flash memory controller automatically detects which host is attempting to access the device and autonomously performs the lane reversal configuration without requiring external intervention. The controller self-manages the switching logic, detecting host presence and configuring the appropriate signal lanes accordingly.
Data Source
AI summary
The present invention provides a memory device including a connector and a flash memory controller. The connector is configured to connect to a first host and a second host. The flash memory controller is configured to select one of the first host and the second host based on a selection signal, and the flash memory controller only processes commands from the selected one of the first host and the second host, and accesses a flash memory module based on the commands.


