Solid State Storage Failure Mode Detection via Read Voltage Increments
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Solid state storage devices face challenges in accurately reading data due to distorted or shifted threshold voltage distribution curves in memory cells, leading to failure modes such as read disturb, data retention, high temperature data retention, F-poly coupling, and endurance failures, which result in erroneous data reading and prolonged read retry processes.
Innovation Solution
A failure mode detection method that adjusts read voltages by specific increments to identify data retention and low/high temperature write failure modes, and an error correction method that selects appropriate read retry voltage sets based on recognized failure modes to shorten the read retry process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read retry operations are performed multiple times with different voltage sets to correct error bits, then data reading accuracy is improved, but the time required for data retrieval increases significantly
Solution Approach 1:
The patent applies preliminary action by performing a first read operation before the main read operation to detect potential failure modes. Based on the result of this preliminary read, the system pre-determines which read retry voltage set to use, avoiding the need to sequentially try multiple voltage sets and significantly reducing the time spent on read retry operations while maintaining data reading accuracy.
2Reliability
If multiple read retry voltage sets are stored and tested to handle different failure modes, then reliability of data retrieval is improved, but device complexity increases
Solution Approach 1:
The patent stores multiple read retry voltage sets in advance, each corresponding to different failure modes. A preliminary read operation detects the actual failure mode, and based on this detection, the system directly selects and applies the appropriate voltage set. This approach maintains high data retrieval reliability while managing device complexity through structured pre-prepared solutions.
Solution Approach 2:
The patent manages multiple voltage sets by parameterizing them according to different failure modes (e.g., read disturb, data retention, F-poly coupling). Each voltage set is characterized by specific voltage parameters tailored to correct errors from particular failure mechanisms. This systematic parameter organization allows the controller to efficiently select the appropriate voltage set based on detected failure mode without excessive complexity.
3Device complexity
If conventional read retry methods are used without failure mode detection, then device complexity is kept low, but productivity decreases due to prolonged read operations
Solution Approach 1:
The patent introduces a preliminary read operation that adds minimal complexity to detect failure modes. This simple detection mechanism enables the system to quickly identify the appropriate read retry voltage set, avoiding time-consuming sequential retries and significantly improving data read speed while maintaining relatively simple control logic.
4Quantity of substance
If threshold voltage distribution curves are distorted or shifted in memory cells, then storage capacity is increased, but measurement precision of read data deteriorates
Solution Approach 1:
The patent addresses threshold voltage distortion by changing the voltage parameter - specifically, applying different read retry voltage sets that are tailored to compensate for voltage shifts caused by high storage capacity operations. Each voltage set is designed to correct errors from specific failure modes that arise when storing more data, thereby maintaining read data accuracy despite increased storage density.
Data Source
AI summary
A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.