SSD Flush Handling for Multi-Step Nonvolatile Data Completion

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Solution Overview

Problem

Existing memory systems face challenges in ensuring data integrity and reliability during power outages or write failures, particularly in nonvolatile memory systems like SSDs, where data that has not been fully written may be lost.

Innovation Solution

A memory system with a memory controller that executes a flush command to read and write valid data from one memory cell to another, ensuring complete nonvolatilization and protection of data through a save and protection operation, using a multi-step write process to finalize data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a multi-step write process is used to ensure data integrity, then data reliability is improved, but write operation time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidwrite operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by executing the first write operation to store initial data in the nonvolatile memory before the second write operation is completed. This ensures that even if the second write operation is interrupted by a power outage, the data is already partially stored and can be recovered, thus improving data reliability while managing write operation time through staged execution

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The write operation is segmented into multiple independent write operations, where each operation writes a portion of the data to the nonvolatile memory. This segmentation allows the system to improve data reliability by ensuring partial data persistence, while the modular structure enables flexible time management and interruption handling for each segment

Inventive Principle:
Principle #1Segmentation

2Reliability

If data is written in multiple operations to ensure completeness, then data integrity is improved, but the complexity of the write process increases

Engineering Contradiction:
Improvedata integrityVSAvoidwrite process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system applies self-service by automatically managing the multi-step write process, including executing multiple write operations, handling interruptions, and recovering data without requiring external intervention. The memory system autonomously ensures data integrity through built-in mechanisms that monitor and complete write operations, thus improving data integrity while masking the underlying complexity from the user

Inventive Principle:
Principle #25Self-service

3Reliability

If the system waits for complete write operation before acknowledging flush command, then data safety is improved, but response time to host decreases

Engineering Contradiction:
Improvedata safetyVSAvoidresponse time to host
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system executes the first write operation as a preliminary action before the flush command completion is acknowledged to the host. This allows the system to improve data safety by ensuring initial data persistence, while the host receives timely acknowledgment and can proceed with subsequent operations, thus balancing data safety with response time

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12602319B2Memory system executing flush command and method of controlling nonvolatile memory upon receiving flush command
Publication Date: 2026.04.14 KIOXIA CORP
  • US12602319B2 patent drawing
  • US12602319B2 patent drawing
  • US12602319B2 patent drawing

AI summary

According to an embodiment, a memory system includes a nonvolatile memory including memory cells and a memory controller coupled to the nonvolatile memory. Each of the plurality of memory cells is configured to store, in a nonvolatile manner, a plurality of bits of data. The memory controller is configured to, in a case where a first memory cell stores valid first bit data as a first bit and does not store data as a second bit, and a second memory cell stores valid second bit data as the first bit and does not store data as the second bit, and upon reception of a flush command from a host, read the second bit data from the second memory cell and write the second bit data read from the second memory cell to the first memory cell as the second bit.