DRAM-less SSD Secure HMB Merkle Tree Validation
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Solution Overview
Problem
Data storage devices face security threats such as replay and playback attacks on host memory buffers (HMBs), which can lead to latency delays, compromising performance.
Innovation Solution
A data storage device controller, coupled to memory devices, fetches commands and entry data from HMBs, conducts simultaneous validity checks using a Merkle tree-based security mechanism, comparing top-level hash signatures to stored signatures, and transmits validity results, ensuring secure operations without the need for DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If HMBs are secured against security attacks using traditional methods, then security reliability is improved, but latency increases by 4 μSec or more
Solution Approach 1:
The system performs preliminary actions by storing cryptographic hashes of HMB data in a chain structure during normal operations. When security validation is needed, the pre-stored hashes enable rapid verification without time-consuming real-time computations, thus maintaining security while minimizing latency impact.
Solution Approach 2:
The patent replaces traditional mechanical security validation methods (sequential data verification) with a cryptographic hash chain system. This substitution allows for faster validation by comparing hash values rather than verifying entire data sets, significantly reducing the latency penalty associated with security checks.
2Object-affected harmful factors
If HMBs are secured against replay and playback attacks, then security against harmful factors is improved, but operational performance deteriorates due to latency delays
Solution Approach 1:
The patent introduces cryptographic hash values as intermediary elements between the HMB data and the validation process. These hash intermediaries enable secure verification of data integrity and authenticity without requiring direct inspection of the actual data, thus protecting against attacks while maintaining operational performance.
Solution Approach 2:
The system performs preliminary cryptographic processing to create and store hash chain structures during normal operations. This preliminary action ensures that when security validation is required, the system can quickly verify data integrity through hash comparison rather than performing time-consuming analysis of the actual data, thereby maintaining high operational performance.
3Measurement precision
If validity checks are conducted sequentially after data fetching, then measurement precision of data integrity is improved, but loss of time increases
Solution Approach 1:
The patent implements continuity of useful action by conducting validity checks in parallel with data fetching operations. The hash validation process runs concurrently with data retrieval, ensuring that data integrity verification is continuously performed without creating sequential bottlenecks, thus maintaining high measurement precision while minimizing time loss.
Data Source
AI summary
Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. The HMB is utilized in place of DRAM in the controller so that the data storage device is DRAM-less. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.