SSD L2P Lookup Acceleration for SMP Collision Handling
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Solution Overview
Problem
Conventional solid-state drives (SSDs) face performance degradation due to collisions in logical-to-physical (L2P) mapping table access operations in symmetric multi-processing environments, leading to resource locking and reduced efficiency.
Innovation Solution
A memory controller with a lookup acceleration circuit and a volatile memory storing a logical-to-physical mapping table, equipped with a message processing circuit and a logical-to-physical mapping table lookup circuit, which includes collision detection and pending queues to manage concurrent requests from multiple processing cores, facilitating efficient memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semaphore is used to lock the L2P mapping table during memory access operations by one processing core, then data consistency is ensured, but other processing cores cannot issue request messages, leading to performance degradation
Solution Approach 1:
The L2P mapping table is divided into multiple segments or regions, allowing different processing cores to access different segments simultaneously. The message processing circuit includes multiple request queues corresponding to different processing cores, enabling parallel access to different portions of the mapping table without requiring a global semaphore lock.
Solution Approach 2:
The message processing circuit acts as an intermediary between processing cores and the L2P mapping table. It manages request queues, detects collisions, and coordinates access to the mapping table, allowing multiple cores to operate concurrently while maintaining data consistency without traditional semaphore-based locking.
2Adaptability or versatility
If firmware-based lookup operations are used in the memory controller, then the system can handle L2P mapping, but processor resources are consumed and collision handling reduces efficiency
Solution Approach 1:
The patent replaces firmware-based software lookup operations with a dedicated hardware lookup acceleration circuit. This circuit includes a message processing circuit and a logical-to-physical mapping table lookup circuit that can perform L2P translations in hardware, significantly improving lookup speed and reducing processor resource consumption.
Solution Approach 2:
The lookup acceleration circuit is self-contained and handles L2P mapping operations autonomously without requiring processor intervention. The message processing circuit independently manages request queues, detects collisions, and coordinates access, freeing the processor from these routine operations.
3Productivity
If multiple processing cores operate in an SMP environment concurrently, then processing throughput is improved, but collisions in LBA ranges cause resource contention
Solution Approach 1:
The message processing circuit dynamically manages request queues for multiple processing cores, adapting to concurrent access patterns. It detects collisions between LBA ranges in real-time and dynamically adjusts queue management, allowing multiple cores to operate concurrently while handling collisions efficiently.
Data Source
AI summary
A memory controller is provided, which includes a processor having a plurality of processing cores, and a lookup acceleration circuit. The lookup acceleration circuit includes a message processing circuit and a logical-to-physical mapping table lookup circuit. The message processing circuit receives request messages from the processing cores using request queues, and puts an incoming request message to a collision pending queue in response to detection of a collision between a first logical address range within the incoming request message and second logical address ranges within message contexts corresponding to active request messages. The logical-to-physical mapping table lookup circuit looks up a logical-physical mapping table in a volatile memory to convert the second logical address ranges into first physical addresses. The message processing circuit performs memory access operations corresponding to the active request messages on the volatile memory using the first physical addresses.