SSD LDPC Decoding Using Candidate Symbol Pruning
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Solution Overview
Problem
The challenge in implementing non-binary LDPC codes in SSD devices lies in the high decoding complexity, particularly for large finite fields, which restricts their practical usage due to the need for high-throughput decoders with moderate silicon area and high speed.
Innovation Solution
A method for decoding read symbols encoded with Q-ary LDPC codes defined over a binary-extension Galois field, utilizing a processing scheme that involves message passing computations between check nodes and variable nodes, with candidate symbols and LLR values stored in matrices to update and refine decoding attempts iteratively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-binary LDPC codes are implemented in SSD devices, then error correction capability is improved, but decoding complexity increases
Solution Approach 1:
The patent segments the finite field GF(Q) into multiple subfields GF(2^m), where Q = 2^(m*r). This segmentation allows the decoder to process symbols by breaking them down into smaller field elements, reducing the complexity of arithmetic operations while maintaining the error correction capability of non-binary LDPC codes.
Solution Approach 2:
The patent changes the parameter representation of symbols from direct Q-ary values to decomposed field elements over subfields. By representing each symbol as a combination of elements from smaller fields, the decoding operations become computationally simpler, addressing the complexity issue while preserving reliability.
2Speed
If high-throughput decoders are designed for non-binary LDPC codes, then decoding speed is improved, but silicon area increases
Solution Approach 1:
The decoder architecture is segmented into multiple processing units that handle different subfields independently. This segmentation enables parallel processing of decoded symbols, increasing throughput while keeping each processing unit compact, thus achieving high speed without excessive silicon area consumption.
Solution Approach 2:
The patent introduces a new dimensional approach by organizing the decoding process across multiple field subdimensions rather than processing entire symbols monolithically. This dimensional decomposition allows for more efficient hardware utilization, achieving high throughput with reduced area by distributing computational load across multiple smaller processing dimensions.
3Reliability
If large finite fields are used for Q-ary LDPC codes, then error correction performance is improved, but hardware requirements increase
Solution Approach 1:
The large finite field GF(Q) is segmented into smaller subfields GF(2^m), allowing the hardware to process complex error correction patterns by breaking them into manageable field element operations. This segmentation maintains the performance benefits of large fields while reducing the hardware complexity required to implement the arithmetic operations.
Solution Approach 2:
The patent changes the parameter representation from direct large-field arithmetic to operations over smaller subfields. This parameter transformation enables the use of simpler, more hardware-efficient arithmetic units while maintaining the error correction performance associated with large finite fields through the mathematical structure of the code.
Data Source
AI summary
A method for decoding, in a solid-state storage device, a read symbol encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r), wherein the read symbol is associated with 2r LLR values each one denoting a symbol probability indicative that the read symbol was equal to a respective possible symbol, the method comprising:(a) associating, with the read symbol, candidate symbols comprising a number of the possible symbols associated with LLR values indicative of highest symbol probabilities;(b) storing the candidate symbols and the associated LLR values in V2C and V_SUM matrices;(c) based on the V2C matrix, performing a check node update procedure to update the C2V matrix;(d1) determining an updating LLR value for each possible symbol associated with the read symbol;(d2) determining, for the V_SUM matrix, an approximated LLR value for each excluded symbol, said determining being based on the LLR value indicative of the lowest symbol probability, and on an offset LLR value;(d3) updating the LLR values and the approximated LLR values of the V_SUM matrix with the respective LLR updating values;(d4) performing step (a) based on the updated LLR values;(d5) performing steps (d2) to (d4) for the V2C matrix;(d6) performing step (b) for both V2C and V_SUM matrices based on the respective candidate symbols and the associated updated LLR values, thereby obtaining updated V2C and V_SUM matrices;(e) determining an outcome of the decoding attempt provided by the updated V_SUM matrix.