SSD LDPC Decoder Switching for Flash Read Latency and Error Correction
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Solution Overview
Problem
Current flash memory technologies face challenges in improving performance, efficiency, and error correction capabilities, particularly in accessing Single-Level Cell (SLC) and Multi-Level Cell (MLC) flash memories, due to increasing data read errors and uncertainties in sensing voltage ranges as technology scales down.
Innovation Solution
A Solid-State Disk (SSD) controller employs Low Density Parity Check (LDPC) decoding, dynamically switching between hard-decision and erasure-decision decoders based on error rates and operational conditions, using single, two, or multiple reads to access flash memory, thereby enhancing error correction and reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hard-decision LDPC decoder is used for SLC flash memory with low BER, then access speed is improved, but error correction capability deteriorates when uncorrectable errors occur
Solution Approach 1:
The system dynamically switches between hard-decision and erasure-decision LDPC decoders based on the detected BER of the flash memory. For SLC flash with BER below threshold, hard-decision decoder provides fast access; for MLC flash or when BER exceeds threshold, erasure-decision decoder ensures reliable error correction. This dynamic adaptation resolves the contradiction between speed and reliability.
Solution Approach 2:
The invention changes the decoding parameter (hard-decision vs. erasure-decision) based on flash memory characteristics and error rates. By adjusting the decoder type according to BER parameters and flash cell type, the system optimizes both access speed and error correction capability for different operating conditions.
2Reliability
If erasure-decision LDPC decoder is used for flash memory with higher BER, then error correction capability is improved, but access latency increases
Solution Approach 1:
The system uses dynamic decoder selection to avoid always using the slower erasure-decision decoder. Instead, it adapts to current flash memory conditions and only employs erasure-decision decoding when necessary for error correction, thereby minimizing latency while maintaining reliability.
Solution Approach 2:
The invention segments the decoding process into two paths: fast hard-decision decoding for good quality data and slower erasure-decision decoding for degraded data. This segmentation allows the system to process most data quickly while applying enhanced error correction only when needed.
3Reliability
If multiple reads are performed to improve error correction, then reliability is improved, but power consumption increases
Solution Approach 1:
The system performs only the necessary number of reads based on detected error conditions. Instead of always performing multiple reads, it uses single read with hard-decision decoding when possible, and only performs additional reads with erasure-decision decoding when errors are detected, thus reducing overall power consumption while maintaining reliability.
Solution Approach 2:
The system uses feedback from initial hard-decision decoding results to determine whether additional reads are necessary. If hard-decision decoding succeeds, no further reads are performed; if it fails, the system triggers erasure-decision decoding with additional reads. This feedback mechanism optimizes power consumption by avoiding unnecessary reads.
Data Source
AI summary
A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.