SSD LDPC Engine Mapping for Parallel Flash Controller Workloads
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Solution Overview
Problem
Current SSD architectures with static mapping of Low Density Parity Check (LDPC) engines to flash controllers result in inadequate parallelism, leading to situations where one LDPC is idle while others are fully occupied, due to the Flash Translation Layer not considering LDPC operations during scheduling.
Innovation Solution
Implementing a dynamic mapping of LDPC engines to flash controllers, allowing the data storage controller to dynamically allocate operations based on priority and workload feedback, ensuring optimal utilization of all LDPC engines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If static mapping of LDPC engines to flash controllers is used, then device structure is simple and easy to implement, but parallelism is insufficient and I/O performance is limited
Solution Approach 1:
The patent implements dynamic mapping of LDPC engines to flash controllers, where the mapping relationship is not fixed but can change based on real-time workload conditions. The controller dynamically determines which LDPC engine handles which flash controller's operations, allowing the system to adapt to varying performance requirements and maximize parallelism utilization.
2Productivity
If Flash Translation Layer schedules operations without considering LDPC status, then scheduling is simple, but LDPC engines cannot operate in parallel efficiently
Solution Approach 1:
The patent introduces a feedback mechanism where the controller monitors the operational status of LDPC engines and uses this information to dynamically adjust the mapping between flash controllers and LDPC engines. This feedback loop ensures that scheduling decisions are made based on real-time system state, maximizing parallelism while maintaining manageable complexity.
3Productivity
If one LDPC engine is idle while others are occupied, then resource allocation is simple, but overall system throughput is reduced
Solution Approach 1:
The patent makes LDPC engines universal resources that can serve multiple flash controllers depending on demand. Instead of dedicating specific LDPC engines to specific flash controllers, any available LDPC engine can handle operations for any flash controller, allowing idle engines to be dynamically assigned to overloaded flash controllers and maximizing system throughput.
Data Source
AI summary
The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.