SSD Controller Map Recycling via Hardware Assist Circuit
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Solution Overview
Problem
Conventional solid-state drive controllers face inefficiencies in data mapping structure recycling, requiring processor-intensive and time-consuming processes that consume significant bandwidth, leading to slow operations and reduced drive lifespan.
Innovation Solution
The implementation of a solid-state drive controller with a processor, cache, and hardware assist circuit that accelerates map recycling by searching the first-level map in hardware, determining valid data without reading headers, and utilizing a two-level map structure to extend drive life, allowing for efficient recycling of erasure candidate blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multi-step processor-intensive process is used to create a list of mapping structures to move prior to block erasure, then the map recycling process is complete and accurate, but the operation speed is slow and processor resources are heavily consumed
Solution Approach 1:
The mapping structure is divided into multiple levels (first level map and second level map). The hardware assist circuit searches only the first level map to identify candidate blocks, while the processor handles the more complex second level map processing. This segmentation allows parallel processing and reduces the time-critical path of the recycling operation.
Solution Approach 2:
The patent replaces processor-based software searching with dedicated hardware assist circuitry that can search the first level map in parallel. This hardware acceleration significantly reduces the time required to identify mapping structures that need to be moved, directly improving map recycling speed without sacrificing accuracy.
2Measurement precision
If conventional search techniques read pages from physical erasure block to create valid and stale candidate lists, then accurate identification of valid data is achieved, but significant bandwidth of the flash device is consumed
Solution Approach 1:
The hardware assist circuit pre-processes and searches the first level map to identify candidate blocks that may contain valid data before the processor performs detailed validation. This preliminary filtering reduces the number of blocks that need to be fully read and processed, thereby reducing flash device bandwidth consumption while maintaining accurate identification of valid data.
Solution Approach 2:
The first level map acts as an intermediary structure between the physical flash blocks and the processor. The hardware assist circuit uses this intermediate representation to quickly identify candidates without directly reading all pages from physical erasure blocks, reducing the bandwidth burden on the flash device while preserving measurement accuracy.
3Device complexity
If the mapping structure is kept at a single level for simplicity, then the map size becomes large and direct physical block searching is more efficient, but the overall recycling process remains processor-intensive and slow
Solution Approach 1:
The mapping structure is segmented into a first level map (stored in cache, searchable by hardware) and a second level map (processed by processor). This segmentation reduces the amount of data that needs to be processed sequentially by the processor, thereby increasing map recycling throughput while maintaining manageable complexity through clear separation of concerns.
Solution Approach 2:
The patent transitions from a single-dimensional flat map structure to a two-dimensional hierarchical structure. The first level map provides quick hardware-accessible indexing, while the second level map provides detailed mapping information. This dimensional change enables parallel processing paths that improve throughput without making the overall system overly complex.
Data Source
AI summary
An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.