SSD Architecture Segregating Memory Dies for Read and Write Isolation

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Solution Overview

Problem

Conventional SSD architectures face issues with high and unpredictable I/O latency due to collisions between I/O operations and maintenance tasks, leading to inconsistent performance, especially in data center environments with high demand and frequent access.

Innovation Solution

The SSD architecture segregates non-volatile memory dies into isolation regions that operate in deterministic and non-deterministic modes, allowing only read operations in one region while performing write and maintenance operations in another, using maintenance counters to manage mode transitions and minimize collisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional SSD architecture uses parallel access across all non-volatile memory dies to maximize bandwidth, then throughput is improved, but I/O latency becomes high and unpredictable due to collisions between I/O operations and maintenance tasks

Engineering Contradiction:
ImprovethroughputVSAvoidI/O latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the non-volatile memory dies into two distinct groups: a first group dedicated to read operations and a second group dedicated to write and maintenance operations. This segmentation prevents collisions between I/O operations and maintenance tasks by isolating them in separate memory die groups, thereby reducing I/O latency while maintaining throughput through parallel operation of both groups.

Inventive Principle:
Principle #1Segmentation

2Reliability

If maintenance operations are performed on non-volatile memory dies, then data reliability is improved, but collisions with host I/O operations occur leading to inconsistent latency performance

Engineering Contradiction:
Improvedata reliabilityVSAvoidI/O latency consistency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts maintenance operations from the general I/O operation pool by dedicating a specific second group of non-volatile memory dies exclusively to maintenance tasks. This extraction ensures that maintenance operations do not collide with host I/O operations on the first group of dies, maintaining data reliability while ensuring consistent I/O latency performance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If all non-volatile memory dies are used for both read and write operations, then storage capacity and parallelism are maximized, but collisions occur at channel controllers and memory dies leading to bottlenecks

Engineering Contradiction:
Improvestorage capacityVSAvoidcollision management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different operational characteristics to different groups of non-volatile memory dies. The first group is optimized for read operations with dedicated read access, while the second group is optimized for write and maintenance operations. This local differentiation reduces collision management complexity by eliminating the need to arbitrate between conflicting operation types on the same dies, while maintaining total storage capacity through the use of all dies.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240362111A1SSD architecture supporting low latency operation
Publication Date: 2024.10.31 KIOXIA CORP
  • US20240362111A1 patent drawing
  • US20240362111A1 patent drawing
  • US20240362111A1 patent drawing

AI summary

In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the first region in the first operation mode.