SSD Parity Error Correction Paging Scheme
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Solution Overview
Problem
Conventional SSD parity operations require substantial SRAM memory area due to increasing NAND page sizes, leading to higher production costs for SSD controllers.
Innovation Solution
Implementing a paging scheme that exchanges portions of the parity component between SRAM and DRAM, allowing only a small amount of SRAM to be dedicated to caching portions of the XOR operation, thereby decoupling XOR SRAM size from NAND page size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SSD parity operations are implemented, then error correction capabilities are maintained, but SRAM memory area requirements increase substantially due to increasing NAND page sizes
Solution Approach 1:
The patent divides the parity computation process into multiple segments by processing one cache line at a time. Instead of loading entire NAND pages into SRAM, the system segments the work into manageable cache line-sized portions that can be processed sequentially, with each segment using only the minimal SRAM needed for that specific portion.
Solution Approach 2:
The patent extracts only the necessary portions of data (cache lines) from the larger NAND page structure into SRAM for processing. By taking out only what is needed for the current computation step rather than the entire data structure, the SRAM footprint is dramatically reduced while still enabling complete parity computation over time.
2Quantity of substance
If larger NAND page sizes are used, then storage capacity increases, but production costs increase due to higher SRAM requirements
Solution Approach 1:
The patent introduces dynamic processing where the system adapts its SRAM usage pattern to handle varying NAND page sizes. By dynamically loading and processing cache lines in sequential batches rather than statically allocating SRAM for the entire page, the system maintains cost-effectiveness across different page size generations.
Solution Approach 2:
The patent changes the operational parameters of the parity computation from page-level operations to cache line-level operations. This parameter change in the granularity of processing allows the system to handle larger NAND pages without proportionally increasing SRAM allocation, thereby controlling production costs.
3Ease of manufacture
If small SRAM area is allocated for parity operations, then production costs are reduced, but the ability to handle large NAND pages efficiently is compromised
Solution Approach 1:
The patent performs preliminary actions by pre-loading cache lines into SRAM before they are needed for parity computation. This allows the minimal SRAM to be fully utilized at each step, maintaining high productivity despite the small total SRAM allocation, as the right data is prepared in advance for each computation cycle.
Solution Approach 2:
The patent ensures continuous useful action by overlapping data transfer and computation operations. While one cache line is being processed in SRAM, the next cache line is being prepared or transferred, eliminating idle time and maintaining high productivity throughout the parity computation process despite limited SRAM resources.
Data Source
AI summary
A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.