SSD Polar Code Extension for Adaptive Error Correction Rates

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Solution Overview

Problem

Solid State Drives (SSDs) based on polar codes lack adaptability in code rate, making them unsuitable for various applications with different stress conditions throughout their lifetime, as changing code rate in polar codes impairs encoding and decoding operations.

Innovation Solution

Implementing a rate-compatible polar code that allows dynamic adjustment of code rate by determining the lowest power of two for codeword length, accessing bit unreliability information to select positions for adding redundant bits, and encoding extended input data with frozen bits to achieve variable code rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If polar codes are used for error correction in SSD devices, then encoding and decoding complexity is reduced compared to LDPC codes, but the code rate cannot be dynamically changed without impairing encoding and decoding operations

Engineering Contradiction:
Improveencoding and decoding complexityVSAvoidcode rate adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The codeword is segmented into information bits and frozen bits at specific positions. The encoder divides the codeword structure into fixed positions (for information bits) and frozen positions (for error correction), allowing the code rate to be adjusted by changing the number of information bits while maintaining the same codeword length and structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The code rate is adjusted by changing the number of information bits (K) while keeping the codeword length (N) fixed. This parameter change allows dynamic adaptation of the code rate to different application requirements without altering the fundamental polar code structure or impairing encoding and decoding operations.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the code rate is changed to adapt to different application stresses, then the SSD device can be adapted to various usage conditions, but traditional puncturing and shortening operations in polar codes impair encoding and decoding operations

Engineering Contradiction:
Improveadaptation to different stressesVSAvoidencoding and decoding operations
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system dynamically adjusts the code rate by varying the number of information bits based on application requirements and stress conditions. The encoder and decoder are designed to handle variable code rates through dynamic parameter adjustment rather than static structure modification, enabling adaptation to different usage conditions without complex operations.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If more bits are stored in a single memory cell to increase storage density, then the storage capacity increases, but the raw error performance deteriorates

Engineering Contradiction:
Improvestorage densityVSAvoidraw error performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Frozen bits are inserted at specific positions in the codeword before data storage to provide error correction capability. This beforehand cushioning against errors enables the system to correct errors that occur in high-density memory cells, compensating for the deteriorated raw error performance through pre-configured redundancy.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11088713B1Solid state drive implementing a rate-compatible polar code
Publication Date: 2021.08.10 MELLONI DIEGO
  • US11088713B1 patent drawing
  • US11088713B1 patent drawing
  • US11088713B1 patent drawing

AI summary

A method for extending a polar code by determining an extension number E such that E/2<N<E whereby N is a number of codeword bits for a polar code that is to be extended and extending a codeword by adding additional redundant/extension bits. Information indicative of a bit unreliability associated with each bit in the codeword is accessed and bit positions with the highest unreliabilities are selected. Input data for an extended codeword is determined by adding a number of redundant bits in the respective selected bit positions.