SSD Pool-Level ECC for High-Bit Error Recovery

The patent segments the error correction process into two distinct stages: (1) device-level ECC decoding that attempts to correct errors locally, and (2) host-level re decoding that handles remaining uncorrectable errors by leveraging redundancy from multiple device reads. This segmentation allows each stage to use appropriately complex algorithms for its specific purpose, rather than requiring the entire system to use the most complex ECC throughout.

The patent introduces an intermediary mechanism where the host system acts as a mediator between multiple storage devices. When device-level ECC fails, the host coordinates reading the same logical address from multiple devices and performs re decoding using combined data. This intermediary approach enables error correction beyond what any single device could achieve alone, without requiring each device to implement excessively complex ECC algorithms.

The patent implements preliminary action by having the storage system pre-configured with multiple devices containing redundant data before read operations begin. When a read failure occurs, the host can immediately initiate re decoding by reading from alternative devices without needing to wait for complex error analysis or external intervention. The redundancy is prepared in advance, enabling rapid fallback to alternative data sources.

The patent employs feedback mechanisms where the host continuously monitors ECC decoding results from each device read. When decoding fails, the system automatically triggers re decoding operations and adjusts its reading strategy based on which devices succeed or fail. This feedback-driven approach allows the system to adaptively optimize read operations, retrying only when necessary and using the minimum number of additional reads required to achieve successful error correction.