SSD Storage Processing Engines for In-Drive Data Acceleration

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Solution Overview

Problem

Moving raw data to a central processing unit (CPU) for processing and analysis is resource-intensive, leading to high capital and operational expenses due to increased energy consumption, network bandwidth, CPU cycles, and memory burden.

Innovation Solution

Implementing a field programmable gate array (FPGA)-based storage processing accelerator (SPA) within a solid state drive (SSD) to offload data processing tasks, utilizing programmable processors or storage processing engines (SPEs) for in-SSD data analysis, which includes pipelined and parallel processing architectures to reduce data movement and resource requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If raw data is moved to CPU for processing and analysis, then data processing capability is improved, but energy consumption and resource burden increase

Engineering Contradiction:

Improvedata processing capabilityVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the data processing function from the CPU and relocates it to the SSD controller. The SSD controller includes a processor and memory that can execute data processing instructions locally, thereby taking out the processing burden from the CPU and reducing the need to move raw data over the network.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the dimension of data processing from centralized CPU processing to distributed processing at the storage layer. By enabling the SSD controller to perform data processing functions, the system moves processing capabilities from one dimension (CPU) to another dimension (storage controller), creating a multi-dimensional processing architecture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If raw data is moved to CPU for processing and analysis, then data processing capability is improved, but network bandwidth and CPU cycles are consumed

Engineering Contradiction:

Improvedata processing capabilityVSAvoidnetwork bandwidth and CPU cycles

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The SSD controller performs data processing functions independently without requiring constant CPU intervention or network bandwidth. The local processor and memory in the SSD controller enable it to service data processing requests autonomously, reducing the burden on shared resources like network bandwidth and CPU cycles.

Inventive Principle:

Principle #25Self-service

3Use of energy by moving object

If data processing is performed in SSD with programmable processors, then energy consumption is reduced, but device complexity increases

Engineering Contradiction:

Improveenergy consumptionVSAvoiddevice complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The SSD controller is designed with a universal processor and memory system that can perform both traditional storage control functions and data processing functions. This multi-functional design allows the same hardware resources to be used for different purposes, reducing the need for dedicated processing components and thereby limiting the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses a simplified processor architecture in the SSD controller that mirrors essential CPU functions without full complexity. The processor can execute data processing instructions using local memory, providing a copied but simplified version of CPU functionality that reduces energy consumption while maintaining acceptable processing capability.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12561057B2Accelerated data processing in solid state drives (SSDs) with host processors and storage processing engines (SPEs)

Publication Date: 2026.02.24 SAMSUNG ELECTRONICS CO LTD

AI summary

A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n−1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.