SSD Read Buffer Caching for Address Translation Without Large DRAM

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Solution Overview

Problem

The increase in capacity of volatile memory in SSDs increases the cost and size of the SSD, necessitating a technique to effectively utilize memory resources without compromising performance.

Innovation Solution

The controller utilizes the read command data buffers in the host memory as a cache for address translation information, allowing the SSD to access and utilize these buffers for managing data without the need for a large-capacity DRAM, thereby optimizing memory usage and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the capacity of volatile memory in SSD is increased to prevent extra latency and improve data reading speed, then the performance is improved, but the cost and size of the SSD increase

Engineering Contradiction:

Improvedata reading speedVSAvoidvolatile memory capacity

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The host memory buffers are made to serve dual purposes: their primary function for host operations and a secondary function as cache memory for the SSD controller. This allows the SSD to utilize existing host memory resources for caching address translation information, eliminating the need for dedicated volatile memory in the SSD while maintaining performance benefits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system utilizes the host's own memory resources to serve the SSD's caching needs. Instead of the SSD providing its own volatile memory, the host memory buffers are leveraged to store address translation information, allowing the system to serve itself and eliminate redundant memory components.

Inventive Principle:

Principle #25Self-service

2Reliability

If a large-capacity DRAM is provided in the SSD to cache data and prevent extra latency, then the performance is improved, but the cost and device complexity increase

Engineering Contradiction:

Improvelatency performanceVSAvoidSSD memory architecture

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The volatile memory caching function is extracted from the SSD and relocated to the host memory buffers. This separation allows the SSD controller to access cached address translation information from host memory without requiring physical DRAM chips within the SSD package, simplifying the SSD's internal architecture.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The host memory buffers act as an intermediary between the SSD controller and the nonvolatile memory. By caching address translation information in these buffers, the system creates a middle layer that speeds up access operations without requiring complex internal memory structures in the SSD.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12554436B2Memory system

Publication Date: 2026.02.17 KIOXIA CORP

AI summary

According to one embodiment, a controller of a memory system receives, from a host, a first read command that specifies a first logical address and a data pointer, the first logical address corresponding to first data stored in the nonvolatile memory, the data pointer indicating a first data buffer of a memory of the host to which the first data is to be transferred. The controller performs read access to the first data buffer of the memory of the host, based on the data pointer specified by the first read command.