NAND Flash BER Estimation for Adaptive SSD Read Flows

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Solution Overview

Problem

Solid-state drives (SSDs) face increased latency and reduced quality of service due to high bit error rates and inter-cell interference, which are exacerbated by high memory cell density and wear and tear, leading to inefficiencies in read operations and error correction processes.

Innovation Solution

The method involves estimating and classifying the bit error rate (BER) of memory cells using threshold voltage distributions, allowing for adaptive read flows that skip or modify decoding stages based on BER thresholds, thereby optimizing read operations and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction codes (ECC) are used to correct read errors in NAND flash memories, then reliability is improved, but read latency increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by selectively executing ECC decoding only when necessary. The controller estimates BER based on threshold voltage distribution and only performs hard decision decoding when the estimated BER exceeds a threshold, avoiding unnecessary decoding operations and reducing read latency while maintaining reliability.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameter of decoding execution from always-executing to conditionally-executing based on BER estimation. By dynamically adjusting whether to perform ECC decoding based on the estimated bit error rate, the system optimizes the balance between reliability and read latency.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple reads at varying threshold voltages are performed to improve read quality, then error correction capability is improved, but read time increases severely

Engineering Contradiction:
Improveread qualityVSAvoidread time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent applies partial action by performing multiple threshold voltage reads only when the estimated BER indicates high error probability. When BER is low, the system performs a single read operation, significantly reducing read time while maintaining read quality when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent performs preliminary BER estimation based on threshold voltage distribution before executing multiple reads. This preliminary action allows the system to decide in advance whether multiple reads are necessary, avoiding unnecessary read operations and reducing overall read time.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If hard decision decoding stages are executed to correct errors, then reliability is improved, but read flow latency is increased

Engineering Contradiction:
Improveerror correctionVSAvoidread flow latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the execution parameter of hard decision decoding from mandatory to conditional based on BER classification. By dynamically adjusting decoding execution based on estimated error rates, the system maintains reliability when errors are likely while minimizing latency when errors are unlikely.

Inventive Principle:
Principle #35Parameter changes

4Quantity of substance

If high memory cell density is used to increase storage capacity, then storage capacity is improved, but inter-cell interference increases leading to higher error rates

Engineering Contradiction:
Improvestorage capacityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements feedback by using the estimated BER (derived from threshold voltage distribution affected by inter-cell interference) to dynamically adjust the read flow and decoding strategy. This feedback mechanism allows the system to compensate for errors caused by high-density inter-cell interference, maintaining reliability despite increased storage capacity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12176044B1Bit error rate estimation and classification in NAND flash memory
Publication Date: 2024.12.24 KIOXIA CORP
  • US12176044B1 patent drawing
  • US12176044B1 patent drawing
  • US12176044B1 patent drawing

AI summary

A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.