SSD Read Speed Prediction Model for Voltage Shifting
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Solution Overview
Problem
Conventional solid state storage devices experience reduced read speed and increased error bits due to shifting threshold voltage distribution curves over time, leading to prolonged error correction processes and retry operations.
Innovation Solution
Incorporating a prediction model and error correction circuit within the control circuit of the solid state storage device, which uses state parameters and machine learning algorithms to dynamically adjust prediction models and determine optimal read operations, thereby reducing read retry rates and maintaining high read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used with default read voltage sets, then error correction capability is maintained, but read speed decreases due to prolonged error correction processes and retry operations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing multiple optimized read voltage sets corresponding to different threshold voltage distribution states before actual read operations occur. When a read operation is needed, the system selects and applies the pre-prepared voltage set that matches the current state, avoiding time-consuming trial-and-error correction processes and thereby maintaining both high read speed and reliable error correction.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the read voltage set based on the detected threshold voltage distribution state. Instead of using a fixed default voltage set, the system adapts the voltage parameters in real-time according to the memory cell state, enabling optimal read performance across different operational conditions and extending device life while maintaining high read speed.
2Device complexity
If default read voltage sets are used for read operations, then device simplicity is maintained, but read accuracy decreases due to shifting threshold voltage distribution curves over time
Solution Approach 1:
The system performs preliminary characterization of the memory device to detect threshold voltage distribution states and pre-determines optimized read voltage sets for each state. This advance preparation allows the control circuit to maintain simple structure while achieving high read accuracy by selecting the appropriate pre-calculated voltage set based on the current device state.
Solution Approach 2:
The patent changes the read voltage parameters according to the detected threshold voltage distribution state. By adjusting voltage levels based on the memory cell state, the system compensates for threshold voltage shifts over time without increasing control circuit complexity, thereby maintaining both simple device structure and high read accuracy.
3Reliability
If multiple retry read voltage sets are stored and used, then error correction reliability is improved, but device complexity increases due to additional storage and control requirements
Solution Approach 1:
Multiple optimized read voltage sets are pre-calculated and stored in the control circuit during device initialization or manufacturing. This preliminary preparation enables the system to have multiple voltage options available without requiring complex real-time calculation capabilities, thereby improving error correction reliability while keeping the control circuit structure relatively simple.
Solution Approach 2:
The system dynamically selects the appropriate read voltage set from the stored multiple options based on the detected threshold voltage distribution state. This dynamic selection capability provides high error correction reliability by matching the voltage set to the current device state, while avoiding the need to store and manage excessively complex voltage configurations.
Data Source
AI summary
A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.