SSD Read Voltage Threshold Adjustment for Bit Error Rate Control
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Solution Overview
Problem
Solid-state drives (SSDs) based on multi-level cell (MLC) NAND devices face performance degradation due to data retention and read disturb stresses, leading to high bit error rates that cannot be corrected by error correcting code (ECC), resulting in burdensome read retry flows.
Innovation Solution
A method and system for dynamically adjusting read voltage thresholds in SSDs by tracking bit error rates and updating them based on stress conditions, using a controller to calculate and store offset values to optimize read thresholds, thereby reducing bit error rates and preventing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If default read voltage thresholds are used for MLC NAND devices, then the system provides high performance with high endurance under normal conditions, but the bit error rate increases under severe stresses such as data retention stress or read disturb stress
Solution Approach 1:
The patent implements dynamic read voltage threshold adjustment by continuously monitoring bit error rates and automatically updating thresholds based on observed stress conditions. The controller transitions from using fixed default thresholds to dynamically adapting thresholds in response to real-time performance degradation, thereby maintaining reliability across varying stress conditions without requiring manual intervention or predefined stress scenarios.
Solution Approach 2:
The patent establishes a feedback mechanism where the controller monitors bit error rates during read operations and uses this information to adjust read voltage thresholds. This closed-loop system continuously measures performance, compares it against acceptable error thresholds, and modifies operational parameters accordingly, enabling the system to self-correct and adapt to changing stress conditions while maintaining data integrity.
2Reliability
If read retry flows are invoked to correct high bit error rates, then data can be recovered, but system performance degrades due to additional read operations
Solution Approach 1:
The patent applies preliminary action by proactively adjusting read voltage thresholds before significant data corruption occurs. By continuously monitoring bit error rates and anticipating threshold drift under stress conditions, the system performs preventive threshold adjustments that maintain data integrity and prevent the need for corrective read retry operations, thereby preserving system performance while ensuring data recovery capability.
3Reliability
If read voltage thresholds are updated dynamically, then bit error rates are reduced under stress conditions, but device complexity increases due to additional tracking and updating mechanisms
Solution Approach 1:
The patent implements self-service by enabling the controller to automatically monitor its own performance through bit error rate tracking and autonomously adjust read voltage thresholds without external intervention. The system serves itself by detecting stress-induced degradation and performing self-correcting threshold updates, thereby maintaining reliability while minimizing the need for complex external monitoring or manual configuration mechanisms.
Data Source
AI summary
Disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. Each of the plurality of memory dies comprises a plurality of blocks. A controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. The controller may determine a bit error rate for the first block based on the data. The controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The read voltage threshold may be stored in the controller.