SSD Controller Higher-Level Redundancy Computation

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Solution Overview

Problem

Current flash memory technologies face challenges in maintaining reliable operation and data integrity due to uncertainties in sensing and changes in electron storage over time, leading to increased probabilities of data corruption, especially as storage capacity and density increase, and existing error correction techniques may not effectively handle failures in NAND flash memory elements.

Innovation Solution

The implementation of dynamic higher-level redundancy mode management with independent silicon elements in SSD controllers, which computes and stores higher-level redundancy information using parity coding and weighted-sum techniques to ensure reliable operation even in the presence of failures, by transitioning between different redundancy modes to maintain data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If higher-level redundancy information is computed using parity coding and weighted-sum techniques, then data integrity and reliability are improved, but computational complexity and processing time increase

Engineering Contradiction:
Improvedata integrityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The redundancy information is divided into multiple units, each protecting a specific portion of data. The system computes and stores separate redundancy units corresponding to different data segments, allowing targeted error correction without processing the entire dataset, thus reducing computational complexity while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-computes and stores higher-level redundancy information during normal operations, so that when errors occur, the correction process can immediately utilize pre-generated redundancy data without performing complex computations in real-time, thereby reducing processing time and computational burden during error correction.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If dynamic redundancy mode management is implemented, then adaptability to failure conditions is improved, but system complexity and control overhead increase

Engineering Contradiction:
Improveadaptability to failure conditionsVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system dynamically transitions between different redundancy modes based on detected failure conditions. When failures are detected, the system adapts by switching to alternative redundancy mechanisms or adjusting redundancy allocation, providing flexibility and adaptability to varying failure scenarios while managing system complexity through automated mode switching.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors storage device health and uses feedback from failure detection to automatically adjust redundancy management strategies. This closed-loop approach allows the system to adapt to changing conditions without requiring complex manual intervention, reducing control overhead while maintaining high adaptability to failure conditions.

Inventive Principle:
Principle #23Feedback

3Duration of action of stationary object

If redundancy information is stored in non-volatile memory, then data persistence is improved, but storage capacity requirements increase

Engineering Contradiction:
Improvedata persistenceVSAvoidstorage capacity
Core Design Contradiction:
Duration of action of stationary objectVSQuantity of substance

Solution Approach 1:

The system stores redundancy information locally within the same non-volatile memory device rather than requiring separate storage resources. By utilizing unused capacity within existing memory blocks and implementing localized redundancy storage, the system maintains data persistence without proportionally increasing overall storage capacity requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The redundancy information is nested within the data structure itself, with redundancy units integrated into the same storage blocks as the protected data. This nested approach allows the system to maintain persistence through the same storage medium without requiring additional separate storage capacity, effectively hiding the redundancy storage within the existing storage infrastructure.

Inventive Principle:
Principle #7Nested doll (Nesting)

4Reliability

If error correction operations are performed, then data reliability is improved, but processing time and latency increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system pre-computes and stores redundancy information during normal read operations, so that when errors are detected, the correction process can immediately utilize the pre-generated redundancy data without performing time-consuming computations, thereby reducing error correction latency while maintaining high data reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

When errors are detected, the system rapidly retrieves and applies pre-computed redundancy information to correct the data, skipping the time-consuming process of real-time redundancy computation. This approach rushes through the error correction process by utilizing预先 prepared redundancy data, significantly reducing processing time while maintaining correction accuracy.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS9183140B2Higher-level redundancy information computation
Publication Date: 2015.11.10 SEAGATE TECH LLC
  • US9183140B2 patent drawing
  • US9183140B2 patent drawing
  • US9183140B2 patent drawing

AI summary

Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.