SSD Write Latency Stabilization via Refresh Throttling
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Solution Overview
Problem
Data storage devices, such as SSDs, face delays in responding to write requests during the refresh write process, which is necessary to prevent data loss in non-volatile memory, leading to performance variations and potential delays in write operations.
Innovation Solution
The implementation of a throttling control mechanism that adjusts the execution frequency of write processes, including the refresh write process, by inserting wait times and managing gear ratios to maintain consistent performance and reduce latency, ensuring that the host write process is not compromised.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh write process is executed with priority to prevent data loss, then data reliability is improved, but write response time deteriorates
Solution Approach 1:
The system performs preliminary actions by detecting the start of a refresh write process before host write requests are affected. By anticipating the refresh operation and preparing threshold values in advance, the system can quickly adjust write execution amounts without waiting for actual conflicts to occur, thus maintaining both data reliability and write response time
Solution Approach 2:
The system implements feedback mechanisms by monitoring the execution status of refresh write processes and adjusting the execution amount of host write processes accordingly. The controller continuously checks whether refresh operations are ongoing and uses this information to dynamically control write throttling, ensuring that data reliability is maintained while minimizing impact on write performance
2Reliability
If the refresh write process is executed with priority, then data reliability is improved, but write performance stability deteriorates
Solution Approach 1:
The system applies dynamics by making the write execution amount adjustable rather than fixed. The controller dynamically changes the execution amount of host write processes based on whether refresh write processes are currently executing. This dynamic adjustment allows the system to adapt to varying conditions, maintaining write performance stability while ensuring data reliability through priority refresh operations
3Loss of time
If write execution amount is reduced during refresh write process, then write latency is stabilized, but productivity deteriorates
Solution Approach 1:
The system applies partial action by selectively reducing write execution amount only during specific periods when refresh write processes are executing, rather than continuously throttling writes. During normal operation, write throughput is maintained at full capacity. This partial application of throttling achieves latency stabilization during critical refresh operations without permanently sacrificing overall productivity
Solution Approach 2:
The system implements periodic action by alternating between different write execution amounts based on the periodic nature of refresh write processes. When refresh operations are not executing, normal write throughput is maintained. When refresh operations are detected, the system periodically adjusts the write execution amount to stabilize latency, creating a rhythmic pattern of throttling that balances performance and reliability
Data Source
AI summary
A storage device includes a nonvolatile memory, a communication interface connectable to an external device, and a control circuit. The control circuit is configured to carry out over an elapsed time period first write operations to write data received through the communication interface in the nonvolatile memory, second write operations to write data stored in a memory region of the nonvolatile memory to another memory region of the nonvolatile memory, and wait operations during which no data are written, read, or erased in the nonvolatile memory, such that the wait operations are carried out during a smaller percentage of the elapsed time period as the elapsed time period becomes longer.