SSD Reset Circuit Delay Mechanism for Data Integrity
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Solution Overview
Problem
The existing solid state drive (SSD) reset mechanism using PCIe buses can lead to data corruption when the host activates a reset signal during ongoing access operations, causing the controlling circuit to reset immediately and potentially losing unrecoverable data.
Innovation Solution
The SSD incorporates a reset circuit with a buffer and a delaying mechanism that detects the reset signal change through I/O ports, temporarily stores data being processed during a delay time, and then resets the physical layer circuit, ensuring data integrity by preventing immediate resets during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the host activates the reset signal directly connected to the physical layer circuit reset terminal, then the reset operation can be performed quickly, but data corruption occurs when reset is activated during ongoing access operations
Solution Approach 1:
The controlling circuit detects the reset signal activation and performs preliminary actions (stopping command reception, storing processed data in buffer) before the physical layer circuit is actually reset. This preliminary intervention prevents data corruption by ensuring data is safely stored before the reset occurs, resolving the contradiction between fast reset and data integrity.
2Loss of time
If the physical layer circuit is reset immediately upon receiving reset signal, then the reset response time is minimized, but data being processed is lost and suffers corruption
Solution Approach 1:
The system performs preliminary data protection actions (storing data in buffer) before the actual reset occurs, minimizing the time window for potential data loss while ensuring data integrity is maintained through the buffering mechanism.
Solution Approach 2:
The buffer acts as an intermediary between the physical layer circuit and the flash array, temporarily holding data during the reset transition. This intermediary structure prevents direct data loss by providing a safe storage location during the critical reset period.
Data Source
AI summary
A solid state drive with a reset circuit includes a controlling circuit, a flash array and a buffer. The controlling circuit includes a physical layer circuit and a first input/output port. The first input/output port is connected with a first reset terminal of a host. The flash array and the buffer are connected with the controlling circuit. When the first reset terminal of the host activates a reset signal, a voltage level of the first input/output port is changed. After a delay time, the voltage level of a second reset terminal of the physical layer circuit is changed and the physical layer circuit is reset.