SSD RLT Oscillator for Host Reference Clock Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Crystal oscillators in storage devices like SSDs incur significant costs, occupy space, and create routing constraints, while host reference clock loss disrupts the operation of storage device components.
Innovation Solution
A reference clock loss tolerant (RLT) oscillator circuit generates a clock based on a host reference clock, maintaining clock accuracy and frequency stability even when the host reference clock is lost, using a combination of relaxation oscillators and frequency locked loops to ensure smooth transitions and PLL lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a crystal oscillator is used to provide clock signal to chipsets, then clock signal stability is ensured, but cost increases, PCB space is consumed, and routing constraints are created
Solution Approach 1:
The patent removes the crystal oscillator from the SSD system and extracts only the essential clock generation function, implementing it through a PLL circuit that can operate with relaxed timing requirements. This eliminates the need for the crystal oscillator component while maintaining clock signal stability for critical operations.
Solution Approach 2:
The PLL circuit is designed to serve multiple functions: it generates clock signals for both high-speed interfaces (requiring strict timing) and low-speed interfaces (tolerant of timing variations), replacing what would traditionally require separate crystal oscillators and clock generation circuits.
2Device complexity
If host reference clock is used to generate output clock, then cost and PCB space are reduced, but operation is disrupted when host reference clock is lost
Solution Approach 1:
The system performs preliminary actions by detecting host reference clock loss in advance and proactively switching to an internal relaxation oscillator before the timing violation occurs. This prevents disruption to the memory die operations rather than reacting after the problem manifests.
Solution Approach 2:
The patent implements a cushioning mechanism by maintaining a relaxed clock signal from the relaxation oscillator that can immediately take over when host reference clock is lost. This preparatory arrangement ensures seamless transition and maintains operation continuity without disruption.
3Reliability
If clock frequency is reduced when host reference clock is lost, then operation continuity is maintained, but data transfer speed decreases
Solution Approach 1:
The system dynamically adjusts clock source selection based on operational conditions: using the high-frequency host reference clock when available for maximum performance, and switching to the relaxation oscillator at reduced frequency only when necessary to maintain operation continuity. This dynamic adaptation optimizes both productivity and reliability.
Solution Approach 2:
The patent applies different clock quality levels to different operational contexts: high-quality synchronized clock from host reference for active data transfer operations, and lower-quality relaxed clock from relaxation oscillator for maintenance operations or when host reference is unavailable. Each context receives appropriate clock quality.
Data Source
AI summary
Aspects of a storage device are provided for producing an oscillator clock from a host reference clock in a storage device lacking a crystal oscillator. The storage device includes a memory die, and an oscillator circuit that generates a clock based on a host reference clock and outputs an output clock to the memory die. While the host reference clock is available, the output clock includes a frequency that is identical to a frequency or a frequency division factor of the host reference clock. In response to loss of the host reference clock, the oscillator circuit reduces the frequency of the output clock to a frequency of the generated clock within a clock cycle following the loss of the host reference clock. In response to re-availability of the host reference clock, the oscillator circuit increases the frequency of the output clock back to the frequency of the host reference clock.