SSD Memory Controller Shared Flash Buffer for QLC Write Delays

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Solution Overview

Problem

Existing memory systems face inefficiencies in utilizing storage regions of nonvolatile memories, particularly in solid state drives (SSDs) due to the long write times and read/write speed decreases associated with high storage density in quad-level cell (QLC) blocks, leading to buffer occupancy issues and delayed data availability.

Innovation Solution

Implementing a shared flash buffer that can be realized as either a QLC buffer or an SLC buffer, allowing for efficient data management by using different write modes (foggy-fine or SLC mode) to reduce buffer occupancy and enhance data readability and storage density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If write data is stored in individual blocks during inactivate commands, then write buffer occupancy increases and storage capacity decreases, but if write data is redirected to a shared buffer, then write buffer occupancy is reduced and storage capacity is improved

Engineering Contradiction:
Improvestorage capacityVSAvoidbuffer management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges individual block buffers into a shared flash buffer that serves multiple blocks. Instead of maintaining separate buffer spaces in each block, the system consolidates buffer functionality into a shared region, reducing total buffer occupancy and increasing user storage capacity while maintaining write operations during inactivate commands.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared flash buffer serves multiple functions: it acts as a write buffer for multiple blocks simultaneously, provides non-volatile storage during inactivate commands, and enables read operations without requiring data to be suspended in individual block buffers. This multi-functional approach reduces overall buffer requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If writes are suspended during inactivate commands, then data completion is ensured, but write operations are interrupted and productivity decreases

Engineering Contradiction:
Improvedata completionVSAvoidwrite operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by redirecting write data to the shared flash buffer before the inactivate command takes effect. This preliminary redirection ensures data is safely stored in a non-volatile region that can be read immediately, allowing write operations to continue without suspension while maintaining data completion reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The shared flash buffer acts as an intermediary between the write operations and the inactivate commands. It receives and holds write data during inactivate periods, mediating between the need for data completion and the desire for continuous write operations, thereby eliminating the need to suspend writes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If extensive buffer allocation is used to maintain write data, then data availability is ensured, but storage density is reduced

Engineering Contradiction:
Improvedata availabilityVSAvoidstorage density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent consolidates buffer allocation from multiple individual blocks into a single shared flash buffer. This merging reduces the total amount of memory dedicated to buffering, as the shared buffer can serve multiple blocks simultaneously, thereby increasing the remaining storage density available for user data while maintaining data availability through non-volatile storage.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12619357B2Memory system controlling nonvolatile memory
Publication Date: 2026.05.05 KIOXIA CORP
  • US12619357B2 patent drawing
  • US12619357B2 patent drawing
  • US12619357B2 patent drawing

AI summary

According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.