SSD Sideband Pin Remapping for Boundary Scan Testing
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Solution Overview
Problem
Conventional memory devices with SSD, PCI-SIG, and SNIA form factors lack pins or pads for boundary scan testing, limiting the ability to detect issues like poor connections and manufacturing defects through electrical testing.
Innovation Solution
Remap sideband signal pins in the memory controller to create a boundary scan interface, allowing for JTAG-like operations to perform electrical testing by reassigning I/O connector pins for boundary scan functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional memory devices use standard form factors (SSD, PCI-SIG, SNIA), then device compatibility and manufacturing simplicity are improved, but the ability to perform boundary scan testing deteriorates due to lack of dedicated pins or pads
Solution Approach 1:
The sideband signal pins are designed to serve dual purposes: during normal operation they carry system management and monitoring signals, while during testing they are remapped to provide boundary scan functionality. This multi-functionality allows the same physical pins to support both standard device operation and specialized testing requirements without adding extra pins.
Solution Approach 2:
The pin functionality is made dynamic through a remapping mechanism that can switch between normal operating mode and boundary scan mode. The memory controller can reconfigure the sideband pins to connect to different internal circuits depending on whether testing or normal operation is required, enabling the system to adapt its electrical connections based on operational context.
2Difficulty of detecting and measuring
If dedicated boundary scan pins are added to memory devices, then testing capability is improved, but device complexity and pin count increase
Solution Approach 1:
Instead of adding dedicated boundary scan pins, the patent reuses existing sideband signal pins for both normal system operations and boundary scan testing. This eliminates the need for additional pins and reduces device complexity while maintaining full testing capability.
Solution Approach 2:
The boundary scan functionality is merged with the existing sideband signal infrastructure. The same physical pins and routing are used for both system management functions and boundary scan operations, combining multiple functions into a single integrated solution rather than implementing them separately.
3Difficulty of detecting and measuring
If sideband pins are remapped for boundary scan operations, then electrical testing effectiveness is improved, but normal system signal communication may be affected
Solution Approach 1:
The pin remapping is implemented dynamically rather than statically. The memory controller can switch between normal mode (where sideband pins carry system management signals) and test mode (where they carry boundary scan signals). This dynamic reconfiguration ensures that normal system operation is not affected during regular use, while full testing capability is available when needed.
Solution Approach 2:
The remapping occurs periodically or on-demand based on operational context rather than being permanent. During normal operation, pins remain in their standard configuration; during testing intervals, they are remapped to boundary scan functionality. This periodic switching ensures system reliability during normal operation while enabling effective testing when required.
Data Source
AI summary
A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.