SSD Power Failure Handling via SLC Mode Switching

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Solution Overview

Problem

Non-volatile memory devices, such as solid state drives, face data integrity issues during sudden power failures when powered by AC-derived power, as they lack advance warning and cannot perform recovery operations in time, unlike battery-powered systems.

Innovation Solution

Implementing a low power write mode that forces all programming operations to single-level cell mode during sudden power failures, allowing the system to preserve data integrity by limiting operations to a single level cell mode until the battery charge level is sufficient to exit back to normal multi-level cell mode operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the system operates in multi-level cell mode for normal programming operations, then storage capacity and productivity are improved, but data integrity reliability deteriorates during sudden power failures

Engineering Contradiction:
Improveprogramming operation speedVSAvoiddata integrity during power failure
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically switches between MLC mode (normal operation) and SLC mode (power failure protection) based on power status detection. The controller monitors battery charge levels and AC power availability, automatically transitioning operational modes to balance performance and reliability according to current power conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the memory cell programming parameter from multi-level (MLC) to single-level (SLC) mode when power failure is detected. This parameter change ensures that only robust single-level programming operations execute during power failure conditions, preventing data corruption while maintaining normal high-speed MLC operations during stable power supply

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the system provides advance warning for battery power loss, then recovery operations can be performed, but the system complexity increases

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidpower management circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The power management circuitry automatically monitors battery charge levels and AC power status without requiring external intervention. The system self-detects power failure conditions and autonomously switches to protective SLC mode or initiates shutdown procedures, eliminating the need for complex user input mechanisms or additional monitoring hardware

Inventive Principle:
Principle #25Self-service

3Reliability

If the system enforces low power write mode during AC power only operation, then data integrity is preserved during sudden power failures, but productivity decreases due to limited programming operations

Engineering Contradiction:
Improvedata integrity during AC power failureVSAvoidprogramming operation throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system applies partial restriction by allowing SLC mode programming operations to proceed during AC power failure conditions, rather than completely halting all programming. This partial action maintains minimal data integrity protection while avoiding total productivity loss, as SLC operations can still complete successfully when power is restored

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9990023B2Systems and methods for handling sudden power failures in solid state drives
Publication Date: 2018.06.05 APPLE INC
  • US9990023B2 patent drawing
  • US9990023B2 patent drawing
  • US9990023B2 patent drawing

AI summary

Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.