SSD Soft-Decision Decoding for Flash Channel Variation
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Solution Overview
Problem
Non-volatile memory (NVM) systems, such as SSD controllers, face challenges in maintaining low latency and extending the lifetime of flash memory due to shifts in threshold voltage distributions, leading to read errors and inefficiencies in error correction.
Innovation Solution
Implementing a method where the SSD controller scrambles data before writing it to NVM, maintaining zero and one counts for each read unit to adjust the read threshold voltage, and using log-likelihood ratio (LLR) soft-decision re-decoding to compensate for channel variations, allowing for efficient error correction without the need for retry reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hard-decision decoding is used for flash memory reads, then device complexity is reduced, but reliability deteriorates due to read errors from threshold voltage shifts
Solution Approach 1:
The patent transforms hard-decision binary data into soft-decision log-likelihood ratios (LLRs) by changing the parameter representation from discrete bits to continuous probability values. This enables the decoder to use magnitude information for more reliable error correction while managing complexity through systematic LLR calculation and compensation methods
Solution Approach 2:
The patent introduces LLR compensation as an intermediary mechanism that adjusts soft-decision values to account for threshold voltage shifts. This compensation layer mediates between the physical channel variations and the decoding process, improving reliability without requiring complete redesign of the decoder architecture
2Reliability
If retry reads are performed to correct read errors, then reliability is improved, but latency increases
Solution Approach 1:
The patent performs preliminary LLR compensation calculations based on predicted threshold voltage shifts before actual decoding is needed. By pre-computing compensation values and preparing adjusted LLR sets in advance, the system reduces the need for time-consuming retry reads while maintaining high error correction capability
Solution Approach 2:
The patent replaces the mechanical retry-read process with a computational LLR adjustment mechanism. Instead of physically re-reading memory cells when errors occur, the system substitutes this with software-based LLR recalculation and compensation, significantly reducing latency while maintaining reliability
3Reliability
If read thresholds are frequently adjusted to track threshold voltage distributions, then reliability is improved, but productivity decreases due to additional processing overhead
Solution Approach 1:
The patent applies partial adjustment by updating LLR compensation parameters selectively rather than for every read operation. By adjusting compensation only when threshold voltage shifts are detected or predicted to exceed certain thresholds, the system maintains read accuracy while minimizing processing overhead and preserving throughput
Data Source
AI summary
In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.