SSD Memory Cell State Compression for Reliable TLC and QLC Storage
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Solution Overview
Problem
The challenge in SSD technology is to reduce the number of Single-Level Cell (SLC) blocks while maintaining data storage reliability and performance, as SLC cells are more expensive and have lower capacity compared to Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quad-Level Cell (QLC) cells, which are less reliable but more cost-effective.
Innovation Solution
A state compression scheme is implemented in SSDs to reduce the number of states in TLC and QLC cells, using encoding schemes to encode data such that fewer states are used for storage, thereby reducing the need for SLC cells, and incorporating redundancy bits to enhance data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SLC cells are used to store critical data, then data reliability is improved, but SSD capacity and cost-effectiveness deteriorate
Solution Approach 1:
The patent applies parameter changes by transitioning TLC/QLC cells from their native multi-state configuration to a compressed 2-state configuration. This is achieved through encoding schemes that map multiple states to two representative states, effectively changing the operational parameters of the memory cells to match SLC reliability characteristics while maintaining the physical TLC/QLC structure
Solution Approach 2:
The patent creates a virtual SLC layer by encoding data into a format that can be reliably stored in TLC/QLC cells. The encoding process generates redundant information that allows reliable data recovery, effectively copying the reliability function of physical SLC cells into the TLC/QLC medium through computational redundancy
2Reliability
If SLC cells are used for critical data storage, then data reliability is improved, but device cost increases
Solution Approach 1:
The patent changes the operational parameters of TLC/QLC cells to function in a 2-state mode, making them suitable for reliable data storage without requiring expensive SLC hardware. This parameter transformation allows cost-effective TLC/QLC cells to provide SLC-level reliability through encoding and state compression techniques
3Reliability
If more SLC cells are allocated, then data reliability is improved, but write amplification factor increases
Solution Approach 1:
The patent makes TLC/QLC cells multi-functional by enabling them to perform both high-capacity storage and reliable critical data storage functions. Through state compression and encoding, the same physical cells can operate in different modes, eliminating the need for separate SLC regions and reducing write amplification associated with maintaining dedicated SLC buffers
Data Source
AI summary
Disclosed is a controller and system for state compression in memory cell. The controller comprises a processor. In one embodiment, the processor is configured to set values of D bits, based on values of M bits. M is an integer greater than 0 and D is an integer greater than 0. The controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory. In another embodiment, the controller is configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, and the controller comprises a processor configured to determine values of the M bits based on the values of the D bits.