SSD Tester Segmentation Reduces Processor Load
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Solution Overview
Problem
Existing SSD testers require significant processor load for generating and comparing test pattern data and Frame Information Structure (FIS) data, making real-time testing of multiple SSDs impossible due to the centralized processing of all functions.
Innovation Solution
The SSD tester divides the functions of generating and comparing test pattern data and FIS data into separate logics, utilizing an embedded processor for control and a test executing unit for hardware-based testing, allowing for real-time testing of multiple storages by distributing the processing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the micro processor performs all functions related to SSD test (generating test pattern, generating FIS data, storing test pattern, reading out data, comparing data), then the test can be controlled centrally, but the processor load becomes excessive and real-time testing of multiple SSDs becomes impossible
Solution Approach 1:
The patent divides the micro processor into two separate units: a control micro processor that generates test patterns and FIS data, and a test execution micro processor that performs data comparison and fail detection. This segmentation reduces the processing load on each unit while enabling real-time testing of multiple SSDs simultaneously.
Solution Approach 2:
The patent extracts the data comparison and fail detection functions from the control micro processor and assigns them to a separate test execution micro processor. This extraction allows the control processor to focus on pattern generation while the execution processor handles data validation, improving overall system throughput.
2Device complexity
If the micro processor performs all functions including generating test pattern and FIS data, then the system structure is simplified, but the processor load is excessive and entire test time increases
Solution Approach 1:
The patent segments the micro processor into a control micro processor for generating test patterns and FIS data, and a test execution micro processor for data comparison. This segmentation reduces the time each processor needs to complete its tasks, thereby reducing the entire test time while maintaining manageable system complexity.
Solution Approach 2:
The patent introduces a new dimension to the system architecture by adding a separate test execution micro processor that operates in parallel with the control micro processor. This dimensional change enables simultaneous execution of different functions, reducing the sequential test time.
3Device complexity
If all test functions are performed by a single micro processor, then the device structure is simpler, but real-time testing of multiple SSDs becomes impossible
Solution Approach 1:
The patent segments the single micro processor into two separate micro processors: a control micro processor that manages test pattern generation and FIS data creation, and a test execution micro processor that handles data comparison and fail detection. This segmentation enables real-time testing of multiple SSDs by allowing parallel processing of different SSDs.
Solution Approach 2:
The patent creates a multi-functional system where the control micro processor generates test patterns and FIS data for multiple SSDs, while the test execution micro processor executes comparisons for multiple SSDs simultaneously. This multi-functionality enables real-time testing of multiple SSDs without increasing overall system complexity excessively.
Data Source
AI summary
Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.