SSD Storage Module Timer-Based Command Execution Control

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Solution Overview

Problem

Solid-state drive (SSD) control modules face limitations in improving writing and access efficiency due to the inability to directly adjust host transmission rates and solid-state memory storage rates, leading to increased storage times and limited data transfer efficiency.

Innovation Solution

A storage module comprising a first memory, a second memory, a staging module, a timing module, and a control module that manages host commands and data transfer between the host and solid-state memory by using timers to optimize command storage and execution, ensuring balanced data transfer rates and minimizing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the control module stops accessing data from the host or signals the host to stop sending data when the buffer is full, then data overflow is prevented, but overall storage times are increased

Engineering Contradiction:
Improvebuffer overflow preventionVSAvoidstorage time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by implementing a timing module that proactively monitors buffer status and predicts when the buffer will be full, allowing the control module to regulate data flow before overflow occurs. This prevents the need to stop accessing data abruptly, thereby reducing storage time while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The timing module continuously provides feedback about buffer status and data flow rates to the control module. This feedback mechanism enables dynamic adjustment of data access patterns, optimizing the balance between preventing buffer overflow and minimizing storage time delays.

Inventive Principle:
Principle #23Feedback

2Productivity

If the control module directly controls transmission rates of the host and storage rates of solid-state memory, then data transfer efficiency is improved, but device complexity is increased

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidcontrol module complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The timing module serves as an intermediary between the host and solid-state memory, mediating the data flow rate control. It monitors and regulates transmission rates without requiring the control module to directly manage both host and memory rates, thereby improving data transfer efficiency while limiting the increase in control module complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The timing module autonomously monitors buffer status and regulates data flow without requiring complex intervention from the control module. This self-service capability allows the system to optimize data transfer efficiency while keeping the control module relatively simple.

Inventive Principle:
Principle #25Self-service

3Productivity

If timers are used to optimize command storage and execution, then access efficiency is improved, but device complexity is increased

Engineering Contradiction:
Improveaccess efficiencyVSAvoidstorage module complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The timing module implements periodic action by using timers to regularly check and optimize command storage and execution. This periodic monitoring and adjustment improves access efficiency through systematic optimization cycles without requiring continuous complex intervention, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9396105B1Method and apparatus for controlling execution of commands to transfer data between a host and a memory in a storage drive
Publication Date: 2016.07.19 MARVELL ASIA PTE LTD
  • US9396105B1 patent drawing
  • US9396105B1 patent drawing
  • US9396105B1 patent drawing

AI summary

A storage module includes a first memory with blocks for storing first and second commands transmitted from a host to a storage module. The staging module determines, based on a first timer, whether the first command has been received from the host. If received, the first command is stored in a first block of the first memory. If not received, the first block is left empty. A timing module starts the first timer when the first block is left empty and starts a second timer for the first block when the first command is stored in the first block. A control module: executes the commands to transfer data between the host and a second memory based on storage of the commands; determines whether a second block is empty; if empty, waits for the second timer to expire; and if not empty, resets the first timer.