SSD Toggle Interface Signal Line Segmentation for Latency Reduction

Solution Overview

Problem

The toggle interface in solid-state drives (SSDs) faces latency issues due to the shared I/O signal line for command, address, and data transfer, preventing simultaneous command and address transfer during data transfer, which delays operations and reduces SSD performance.

Innovation Solution

The implementation of an interface circuit that uses separate signal lines for command, address, and data transmission, allowing for concurrent transfer of commands and addresses during data transfer using a two-lines interface mode, enabling improved communication between the memory controller and nonvolatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a shared I/O signal line is used for command, address, and data transfer in the toggle interface, then device complexity is reduced, but latency increases and productivity deteriorates due to inability to transfer commands during data transfer

Engineering Contradiction:

Improvesignal line configurationVSAvoidlatency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent segments the signal line functionality by introducing separate command/address signal lines (CA0-CA7) from the data signal lines (DQ0-DQ7). This segmentation allows command and address transfers to occur independently from data transfers, eliminating the latency caused by shared line contention while maintaining manageable system complexity through dedicated line assignments.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds a new dimension to the interface by utilizing additional signal lines that were previously unused or underutilized. By allocating separate CA0-CA7 lines for command/address operations while maintaining the existing DQ0-DQ7 data lines, the system transitions from a single-dimensional shared interface to a multi-dimensional parallel interface, enabling simultaneous operations without significantly increasing overall complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Device complexity

If a shared I/O signal line is used for command, address, and data transfer, then device complexity is reduced, but productivity decreases due to sequential operation requirements

Engineering Contradiction:

Improvesignal line configurationVSAvoidSSD performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent segments the signal line functionality by introducing separate command/address signal lines (CA0-CA7) from the data signal lines (DQ0-DQ7). This segmentation allows command and address transfers to occur independently from data transfers, eliminating the latency caused by shared line contention while maintaining manageable system complexity through dedicated line assignments.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent enables continuous useful action by allowing command and address transfers to proceed simultaneously with data transfers through the dedicated CA0-CA7 lines. This eliminates idle waiting periods where the interface must switch between operations, ensuring that the SSD controller can continuously issue commands and addresses without interruption from data transfer operations, thereby maintaining high productivity.

Inventive Principle:

Principle #20Continuity of useful action

3Loss of time

If separate signal lines are used for command, address, and data transmission, then latency is reduced and productivity is improved, but device complexity increases

Engineering Contradiction:

ImprovelatencyVSAvoidsignal line configuration

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent adds a new dimension to the interface by utilizing additional signal lines that were previously unused or underutilized. By allocating separate CA0-CA7 lines for command/address operations while maintaining the existing DQ0-DQ7 data lines, the system transitions from a single-dimensional shared interface to a multi-dimensional parallel interface, enabling simultaneous operations without significantly increasing overall complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11481157B2Electronic apparatus and transfer method

Publication Date: 2022.10.25 KIOXIA CORP

AI summary

According to one embodiment, an electronic apparatus includes an interface circuit connectable to a first signal line, a second signal line, and a third signal line, and a controller. Before transmitting data using the first signal line, the controller is configured to transmit a first command using the first signal line while transmitting a first control signal using the second signal line, and transmit a first address using the first signal line while transmitting a second control signal using the third signal line. While transmitting the data using the first signal line, the controller is configured to transmit at least one of a second command and a second address using the second signal line and the third signal line.