SSD Token-Based Resource Allocation for Accelerator Conflicts
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Solution Overview
Problem
Solid State Drive (SSD) devices face challenges in efficiently allocating resources for accelerators, leading to suboptimal performance and computational workload offloading, as existing technologies lack effective methods to dynamically manage non-volatile memory and bus resources for various data types and throughput requirements.
Innovation Solution
The implementation of a system that dynamically assigns portions of the non-volatile memory array to accelerators as caches, allowing direct access and sharing of resources, with a token management system to minimize conflicts and optimize storage device performance by allocating cache memory and bus resources based on computational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If accelerators are added to SSD devices to offload computational workload, then processing capability and computational throughput are improved, but resource allocation complexity and device complexity increase
Solution Approach 1:
The patent introduces a resource manager as an intermediary component that mediates between accelerators and non-volatile memory resources. The resource manager dynamically allocates cache memory and bus bandwidth to different accelerators based on their computational needs, thereby resolving the complexity of direct resource management while maintaining high computational throughput.
Solution Approach 2:
The patent implements dynamic resource allocation where the resource manager continuously monitors accelerator performance and adjusts cache memory size and bus bandwidth allocation in real-time. This dynamic adaptation allows the system to optimize computational throughput while managing resource allocation complexity through automated feedback mechanisms.
2Speed
If non-volatile memory is allocated as cache for accelerators, then data access speed and computational efficiency are improved, but available storage capacity for host data is reduced
Solution Approach 1:
The patent segments the non-volatile memory array into multiple independent cache regions, each dynamically assigned to specific accelerators. The resource manager can allocate different portions of the memory array to different accelerators based on computational workload, allowing high-speed cache access for accelerators while preserving remaining capacity for host storage needs.
Solution Approach 2:
The patent implements dynamic memory allocation where cache memory size for each accelerator is adjusted based on real-time computational requirements. When accelerators require high performance, larger memory portions are allocated as cache; when computational workload decreases, memory is reallocated to host storage, thus balancing data access speed with available storage capacity.
3Productivity
If multiple accelerators share bus resources, then device utilization and productivity are improved, but resource conflicts and access delays increase
Solution Approach 1:
The patent implements preliminary bus bandwidth allocation where the resource manager pre-allocates bus bandwidth to accelerators based on their computational workload requirements before data transfer operations begin. This preliminary allocation reduces contention and access delays by ensuring that accelerators have guaranteed bandwidth availability when needed.
Solution Approach 2:
The patent implements dynamic bus bandwidth allocation where the resource manager continuously monitors bus utilization and adjusts bandwidth allocation to different accelerators in real-time. This dynamic adjustment allows multiple accelerators to share bus resources efficiently, maintaining high device utilization while minimizing access delays through adaptive resource distribution.
Data Source
AI summary
Solid State Drive devices with hardware accelerators and methods for apportioning storage resources with tokens in the SSD are disclosed. SSDs typically comprise an array of non-volatile memory devices and a controller which manages access to the memory devices. The controller may also comprise one or more accelerators to either improve the performance of the SSD itself or to offload specialized computation workloads of a host-computing device. Different accelerators may be dynamically assigned portions of the non-volatile memory array according to the type of data being accessed and/or the throughput required. Provision is also made for the data to be accessed directly by the accelerators bypassing the controller. The accelerators may also share data bus bandwidth and resources with each other or the storage device controller. To minimize conflicts and improve the storage device performance, a system of tokens for both cache memory and bus bandwidth is used to dynamically assign these resources.