SSD Transfer Buffer Utilization via NAND Page Buffers
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Solution Overview
Problem
Misplacement errors are a significant issue in Multi-Level Cell (MLC) and Triple Level Cell (TLC) NAND flash memory due to the lack of internal error checking and correction mechanisms, leading to errors when writing upper page data after reading and correcting lower page data.
Innovation Solution
Implementing a transfer buffer with an ECC engine in the SSD controller to perform error checking and correction on lower page data before writing upper page data, and using NAND page buffers to store upper page data, thereby reducing the size requirements of the transfer buffer and minimizing misplacement errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transfer buffer is used to store both lower page data and upper page data simultaneously for error correction, then misplacement errors are reduced, but the transfer buffer size increases
Solution Approach 1:
The patent divides the data storage function into two separate buffers: a first buffer for lower page data and a second buffer for upper page data. This segmentation allows each buffer to be optimized independently and reduces the total buffer size requirement compared to a single buffer needing to hold both types of data simultaneously.
Solution Approach 2:
The patent introduces a page buffer as an intermediary component between the NAND flash memory and the transfer buffer. The page buffer temporarily stores page data during read operations, allowing the transfer buffer to focus solely on storing corrected lower page data without needing to accommodate upper page data, thus reducing transfer buffer size requirements.
2Reliability
If error checking and correction is performed on lower page data before writing upper page data, then misplacement errors are corrected, but the writing process time increases
Solution Approach 1:
The patent performs error checking and correction on lower page data before the upper page data writing operation begins. By completing the ECC process in advance on the lower page data, the system ensures that when upper page data is written, the lower page data is already corrected and ready, preventing misplacement errors without delaying the overall write operation.
Solution Approach 2:
The patent maintains continuous data flow by using the page buffer to hold upper page data while the transfer buffer simultaneously processes lower page data for ECC. This overlapping of operations allows error correction to proceed in parallel with data preparation, ensuring continuous useful action without unnecessary delays.
3Quantity of substance
If a large transfer buffer is used to accommodate both lower and upper page data, then data storage capacity is sufficient, but the device complexity increases
Solution Approach 1:
The patent segments the transfer buffer into two distinct buffers: a first buffer for lower page data and a second buffer for upper page data. This segmentation simplifies buffer management by allowing independent control and allocation of each buffer, reducing the complexity compared to managing a single large buffer that must handle both data types simultaneously.
Solution Approach 2:
The page buffer acts as an intermediary that simplifies the data flow between NAND flash memory and the transfer buffer. By introducing this intermediate storage layer, the system reduces the complexity of coordinating data transfers and error correction operations, as the page buffer automatically manages temporary data storage during read operations.
Data Source
AI summary
A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.