Multi-Page Translation Units for SSD Address Mapping With Bad Blocks
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Solution Overview
Problem
Increasing SSD storage capacity requires larger amounts of volatile memory (DRAM) for efficient address translation, leading to increased size, power consumption, and manufacturing costs, while existing techniques like L2P table swapping and large translation units face challenges in managing non-sequential pages and bad blocks.
Innovation Solution
Implementing dynamic reservation and unreservation of memory pages to form multi-page translation units, allowing efficient read and write address translation by excluding or including pages based on bad blocks and page indices, reducing the need for DRAM and optimizing memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger amounts of volatile memory (DRAM) are used for address translation to support increased SSD storage capacity, then address translation efficiency is improved, but device size, power consumption, and manufacturing costs increase
Solution Approach 1:
The patent divides the address translation function into segments: frequently accessed translation entries are kept in DRAM, while less frequently accessed entries are stored in non-volatile memory. This segmentation allows the system to maintain high translation efficiency for common operations while reducing overall DRAM requirements and associated power consumption.
Solution Approach 2:
The patent implements different quality levels of memory for different translation needs. Critical and frequently accessed translation entries receive high-quality fast DRAM access, while other entries use lower-quality but more energy-efficient non-volatile storage. This local quality differentiation optimizes the balance between translation speed and power consumption.
2Productivity
If larger amounts of volatile memory (DRAM) are used for address translation to support increased SSD storage capacity, then address translation efficiency is improved, but device size increases
Solution Approach 1:
By segmenting the translation address space into active and inactive portions, the patent enables the active portion to be cached in smaller DRAM while the inactive portion resides in non-volatile memory, thereby reducing the total DRAM capacity required and consequently reducing device size.
Solution Approach 2:
The patent introduces a temporal dimension to address translation by using wear-leveling and translation caching strategies that move entries between DRAM and non-volatile memory based on access patterns, effectively reducing the spatial requirement for DRAM while maintaining translation efficiency.
3Productivity
If larger amounts of volatile memory (DRAM) are used for address translation to support increased SSD storage capacity, then address translation efficiency is improved, but manufacturing costs increase
Solution Approach 1:
The patent segments the memory hierarchy into DRAM and non-volatile memory components, allowing manufacturers to use smaller, less expensive DRAM capacities while achieving acceptable translation performance through intelligent caching and wear-leveling algorithms, thereby reducing overall manufacturing costs.
Solution Approach 2:
The patent dynamically changes operational parameters such as translation cache size, wear-leveling thresholds, and entry eviction policies to optimize performance for different workloads, enabling the system to maintain high translation efficiency with reduced DRAM capacity and lower manufacturing costs.
4Quantity of substance
If L2P table swapping is used to manage limited DRAM, then DRAM usage is optimized, but additional memory operations are required increasing complexity
Solution Approach 1:
The patent implements self-service mechanisms where the translation cache automatically manages its own contents through wear-leveling algorithms and access-pattern-based eviction policies, reducing the need for complex external management and minimizing additional memory operations while optimizing DRAM usage.
5Quantity of substance
If large translation units are used to reduce L2P table size, then DRAM requirements are reduced, but managing non-sequential pages and bad blocks becomes more difficult
Solution Approach 1:
The patent employs self-service wear-leveling algorithms that automatically handle the complexities of non-sequential page management and bad block avoidance within large translation units, distributing write operations evenly across available pages and dynamically adapting to page status without requiring complex external management.
Solution Approach 2:
The patent dynamically adjusts translation unit parameters such as entry size, page allocation strategies, and bad block skip patterns based on workload characteristics and memory status, simplifying the management of non-sequential pages and bad blocks while maintaining reduced DRAM requirements.
Data Source
AI summary
In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.