SSD Two-Level Parity for High-Temperature Data Reliability
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Solution Overview
Problem
Existing memory devices face challenges in maintaining data reliability at elevated temperatures, where errors can occur due to noise, voltage disturbances, and retention loss.
Innovation Solution
Implementing two levels of parity protection for stored data, where a second level of parity data is created among codewords already protected by a first level, providing enhanced error correctability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes are used, then data storage is possible, but data reliability deteriorates at elevated temperatures
Solution Approach 1:
The patent segments the error correction process into two distinct levels: a first error correction code applied to individual data units, and a second error correction code applied to multiple codewords grouped together. This segmentation allows each level to handle different types and magnitudes of errors, particularly effectively addressing temperature-induced errors that traditional single-level codes cannot correct reliably
Solution Approach 2:
The patent employs a composite error correction structure combining two different error correction codes with varying strengths and characteristics. The first ECC provides baseline protection, while the second ECC provides enhanced protection for grouped codewords. This composite approach creates a more robust error correction system that maintains data reliability under elevated temperature conditions where traditional single-code systems fail
2Reliability
If more error correction bits are added, then error correctability improves, but device complexity increases
Solution Approach 1:
The patent divides the error correction burden into two sequential stages: first applying a simpler ECC to individual data units, then applying a second ECC to groups of codewords. This segmentation allows the system to achieve high error correctability without requiring a single overly complex code, as each stage handles a manageable portion of the correction task
Solution Approach 2:
The patent applies error correction in partial steps rather than attempting to correct all errors in a single pass. The first ECC handles initial errors, and the second ECC handles remaining errors in grouped codewords. This multi-stage partial action approach achieves superior error correctability while keeping each individual coding stage relatively simple
Data Source
AI summary
After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.