SSD/UFS Erasure-Correction Hardware Using Neural Matrix Inversion
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Solution Overview
Problem
Conventional erasure correction methods are computationally complex and inefficient due to high-order matrix inversion, which hinders the effective correction of erasures in coding theory, especially in systems requiring rapid and efficient decoding of erasures in distributed storage and communication systems.
Innovation Solution
A hardware architecture utilizing a neural network to approximate the inverse of a parity-check matrix, which iteratively updates and refines the matrix inversion process, reducing computational load by using a recurrent or convolutional neural network trained with reinforcement learning to determine new erasures and correct the matrix, thereby accelerating the erasure correction process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional matrix inversion methods are used for erasure correction, then accurate correction can be achieved, but computational complexity increases to O(dim(A)³)
Solution Approach 1:
The patent replaces the conventional mechanical matrix inversion process with a neural network system that learns to approximate the inverse matrix through training. The neural network substitutes the direct computational inversion mechanism with a learned approximation model, reducing the computational burden from O(dim(A)³) to O(dim(A)²) per iteration while maintaining correction accuracy through iterative refinement.
Solution Approach 2:
The patent performs preliminary training of the neural network offline using training datasets containing various matrix inversion problems. This preliminary action pre-loads the network with inversion knowledge, so that during actual erasure correction, the network can quickly approximate inverses without performing full inversion computations, thus reducing real-time computational complexity.
2Productivity
If iterative neural network approximation is used to reduce computational load, then processing speed improves, but the number of iterations required may increase
Solution Approach 1:
The patent implements a feedback mechanism where the neural network's approximation is evaluated against the actual matrix product, and the error information is fed back to update the network's weights through gradient descent. This feedback loop allows the system to converge to accurate solutions while maintaining fast per-iteration processing, balancing speed and iteration count by continuously improving approximation quality.
3Device complexity
If neural network approximation is used instead of exact matrix inversion, then computational complexity reduces, but approximation error may affect correction precision
Solution Approach 1:
The patent makes the system dynamic by allowing the neural network to iteratively refine its approximation. Rather than using a static single-pass approximation, the network adapts its weights across multiple iterations based on feedback from the actual matrix product, enabling the system to transition from coarse approximation to precise correction dynamically.
Solution Approach 2:
The patent performs more iterations than the minimum single inversion would provide, using multiple refined approximations to converge to the exact solution. This excessive action of performing repeated approximations with feedback ensures that the final result achieves exact precision while each individual step maintains low computational complexity.
Data Source
AI summary
A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix H1 of columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix H2 of columns of H located on non-erased coordinates of code C; a neural network that calculates matrix J1 that is an approximate inverse of matrix H1. The matrix J1 is used to determine new erasures in the parity matrix H and new erased coordinates. Matrices H1 and H2 are updated, and the updated H1 is provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J1, matrix H2, and a non-erased part of codeword C.