SSD Variable Plane Programming with Dual mWCCBs for Lower Buffer Demand

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Solution Overview

Problem

Fixed multi-plane programming in SSDs leads to increased buffer size requirements and potential deadlocks due to varying write frequencies and data amounts across data streams, necessitating large on-chip capacitance and vulnerability to power loss.

Innovation Solution

Implementing a system with dual minimum write cache control buffers (mWCCBs) and variable plane programming to manage data streams, allowing partial data storage in multiple planes and reducing volatile buffer size requirements through coordinated release and reuse of cache buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fixed multi-plane programming accumulates data to fill all pages of a wordline before writing, then data integrity is maintained, but buffer size increases and deadlock risk increases

Engineering Contradiction:
Improvedata integrityVSAvoidbuffer size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the wordline into multiple planes and allows independent programming of each plane with sufficient data, rather than requiring all planes to be filled. This segmentation enables partial wordline programming, reducing the buffer size needed from needing to hold all pages to only needing to hold enough data for one plane at a time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements partial programming where data is written to only those planes that have sufficient data available, rather than waiting to fill all planes. This partial action approach allows the system to proceed with programming using available data, reducing buffer requirements while maintaining data integrity through coordinated multi-plane operations.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If buffer size is increased to accommodate varying data amounts across 32 data streams, then data loss during power loss is prevented, but on-chip capacitance increases

Engineering Contradiction:
Improvepower loss protectionVSAvoidon-chip capacitance
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

By segmenting the programming operation into plane-level independent transactions, the system only needs to buffer data for a single plane (one page worth) rather than accumulating data for all planes across multiple wordlines. This reduces the required on-chip capacitance while maintaining protection against power loss through coordinated multi-plane programming.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic buffer management where the buffer size adapts to the actual programming needs based on data availability across multiple streams. Rather than allocating fixed large buffers for all possible scenarios, the system dynamically uses only the necessary buffer space for current plane programming operations, reducing overall capacitance requirements.

Inventive Principle:
Principle #15Dynamics

3Productivity

If fixed multi-plane programming waits to fill all pages before writing, then programming efficiency is optimized, but latency increases due to deadlock

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the programming workflow into independent plane-level operations that can proceed as soon as sufficient data is available for each plane, rather than requiring global completion of all planes. This eliminates the deadlock condition where the system waits for complete wordline filling, reducing latency while maintaining efficient programming through coordinated multi-plane execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary data placement into plane-specific buffers as data arrives from multiple streams, preparing data for immediate plane programming when sufficient data is available. This preliminary action allows the system to proceed with programming without waiting for complete wordline accumulation, reducing latency while maintaining programming efficiency through advance preparation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260029951A1Configurable data placement with variable plane programming
Publication Date: 2026.01.29 MICROCHIP TECHNOLOGY INC
  • US20260029951A1 patent drawing
  • US20260029951A1 patent drawing
  • US20260029951A1 patent drawing

AI summary

A data storage system includes a memory device and a controller. The memory device includes a set of planes and a wordline including a set of pages. The controller includes a first and second minimum write cache control buffer (mWCCBs), processor(s), and a memory. The memory includes instructions, that when executed the processor(s), cause the processor(s) to: determine that an amount of outstanding data of a data stream is not sufficient to occupy the set of planes; store a first portion of the outstanding data in the first mWCCB; release the first portion to the memory device; in coordination with the release of the first portion of the outstanding data, store a second portion of the outstanding data in the second mWCCB; release the second portion to the memory device; and write the first and second portions of the outstanding data to a subset of the set of pages.