Volatile Memory Controller for SSD Transaction Merging
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Solution Overview
Problem
Current storage devices, particularly in enterprise servers, face challenges in achieving high operation speed due to increasing bandwidth demands and high power consumption, with traditional SSD controllers relying on internal memory or DRAM as data buffers, which require expensive error correction codes for data stability.
Innovation Solution
A storage device with a volatile memory controller that includes an error correction circuit and a data aggregator to merge write transactions based on a burst length, enabling efficient error correction and improved operation speed by processing continuous address write transactions, and a non-volatile memory device with a main memory for temporary data storage and metadata management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used as data buffer in SSD controller, then operation speed is improved, but power consumption increases and cost increases due to expensive ECC function
Solution Approach 1:
The patent uses volatile memory (which loses data when power is cut off) instead of expensive non-volatile memory with ECC, accepting the trade-off of data loss in exchange for lower cost and power consumption. The system design accounts for this by implementing recovery mechanisms that can restore data from the non-volatile memory device.
Solution Approach 2:
The patent extracts the ECC function from the memory controller and implements it separately in the host system or through software-based error correction, allowing the use of simpler, cheaper volatile memory in the SSD controller while still providing error correction capabilities when needed.
2Ease of manufacture
If internal memory is used as data buffer in SSD controller, then cost is reduced, but operation speed deteriorates
Solution Approach 1:
The patent employs volatile memory as the data buffer, which is cheaper than non-volatile memory with ECC, while accepting that data may be lost when power is interrupted. The system recovers from such losses using the non-volatile memory device as persistent storage.
3Reliability
If write transactions are processed individually, then data accuracy is maintained, but operation speed deteriorates due to increased transaction overhead
Solution Approach 1:
The patent merges multiple individual write transactions into a single batched transaction, reducing the overhead of processing each transaction separately. This improves operation speed while maintaining data accuracy through the error correction circuit that validates the merged transaction data.
Data Source
AI summary
The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.